无我

评论

# re: VHDL语言数字钟 2007-12-07 21:49 454

1545  回复  更多评论   

# re: VHDL语言数字钟 2007-12-07 21:49 454

87  回复  更多评论   

# re: VHDL语言数字钟 2007-12-11 21:11 rgh

xiexie   回复  更多评论   

# re: VHDL语言数字钟 2007-12-24 00:54 余波

这东西太好了  回复  更多评论   

# re: VHDL语言数字钟 2007-12-24 01:44 余波

要是能把星期加上就好了
呵呵，这个嘛，我自己可以完成的喔
不过有点不明白，你为什么没有用防抖动啊
还有就是在仿真的时候结果不是很明显喔！
以后有问题可以请教你吧！QQ＝＝312097045请附（FPGA）  回复  更多评论   

# re: VHDL语言数字钟 2007-12-29 12:41 Tim

行，一起交流！QQ:370511754  回复  更多评论   

# re: VHDL语言数字钟 2008-11-07 01:03 关系字

n你的问提也是我现在的问题啊 我也在做数字钟 我的方法是可以让抱时间1点响一下 2点两下.......还有一写附加的报时功能 可能是分频太多 有些可以信号重叠拉无法报时 报时模块全都没有响我想问怎么解决   回复  更多评论   

# re: VHDL语言数字钟 2008-12-14 05:52 无名小卒

请教一下，那个源程序用什么打开啊，我是VHDL初学者，我安装了max+plus2 但是打不开，怎么打开呢，  回复  更多评论   

# re: VHDL语言数字钟 2009-01-25 09:44 Tim

各位朋友，大家好！谢谢大家的关注。这是我以前大学时做的电子课程设计，现在工作了，一方面是没有从事硬件方面的；另一方面时间太忙。对不起呀！
关于打不开的问题，可能还是具体硬件不对应，我找到了以前的文档，这里附带提供，有需要的一起参考吧@无名小卒
  回复  更多评论   

# re: VHDL语言数字钟 2009-04-22 08:57 acetuo

老大，你的秒表运行不起来。在秒表状态下，00 000，后面一个0一直闪，为8，可数字不进行加哟，进位，这是为啥呀。
cfungt@gmail.com
谢谢老大！！！  回复  更多评论   

# re: VHDL语言数字钟 2009-05-16 16:52 baby

我也在做数字钟的设计，波形老出不来，你能帮我看看程序有什么问题吗、。谢谢咯~~是用Quartus II做的。  回复  更多评论   

# re: VHDL语言数字钟 2009-05-16 17:00 baby

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk:in std_logic;
clr:in std_logic;
en:in std_logic;
mode:in std_logic;
inc:in std_logic;

seg7:out std_logic_vector(6 downto 0);
scan:out std_logic_vector(5 downto 0);
sec,min:out integer range 0 to 59;
hour:out integer range 0 to 23);
end;
architecture one of clock is
signal state:std_logic_vector(1 downto 0);
signal qhh,qhl,qmh,qml,qsh,qsl:std_logic_vector(3 downto 0);
signal data:std_logic_vector(3 downto 0);
signal cnt:integer range 0 to 5;
signal clk1khz,clk1hz,clk2hz:std_logic;
signal blink:std_logic_vector(2 downto 0);
signal sec1,min1:integer range 0 to 59;
signal hour1:integer range 0 to 23;
signal inc_reg:std_logic;
begin
process(clk)
variable count:integer range 0 to 9999;
begin
if clk 'event and clk='1' then
if count=9999 then clk1khz<=not clk1khz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 499;
begin
if clk1khz 'event and clk1khz='1' then
if count=499 then clk1hz<=not clk1hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(clk1khz)
variable count:integer range 0 to 249;
begin
if clk1khz 'event and clk1khz='1' then
if count=249 then clk2hz<=not clk2hz;count:=0;
else count:=count+1;
end if;
end if;
end process;
process(mode,clr)
begin
if clr='1' then
state<="00";
elsif mode 'event and mode='1' then
state<=state+1;
end if;
end process;
process(clk1hz,state,en,clr)
begin
if clr='1' then
hour1<=0;
min1<=0;
sec1<=0;
elsif clk1hz 'event and clk1hz='1' then
case state is
when "00"=>if sec1=59 then sec1<=0;
if min1=59 then min1<=0;
if hour1=23 then hour1<=0;
else hour1<=hour1+1;
end if;
else min1<=min1+1;
end if;
else sec1<=sec1+1;
end if;
when "01"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if hour1=23 then
hour1<=0;
else hour1<=hour1+1;
end if;
end if;
else inc_reg<='0';
end if;
when "10"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if min1=59 then
min1<=0;
else min1<=min1+1;
end if;
end if;
else inc_reg<='0';
end if;
when "11"=>if inc='1' then
if inc_reg='0' then inc_reg<='1';
if sec1=59 then
sec1<=0;
else sec1<=sec1+1;
end if;
end if;
else inc_reg<='0';
end if;
end case;
end if;
end process;
  回复  更多评论   

# re: VHDL语言数字钟 2009-05-16 17:01 baby

process(state,clk2hz)
begin
case state is
when"00"=>blink<="000";
when"01"=>blink<=(2=>clk2hz,others=>'0');
when"10"=>blink<=(1=>clk2hz,others=>'0');
when"11"=>blink<=(0=>clk2hz,others=>'0');
end case;
end process;
process(sec1)
begin
case sec1 is
when 0|10|20|30|40|50=>qsl<="0000";
when 1|11|21|31|41|51=>qsl<="0001";
when 2|12|22|32|42|52=>qsl<="0010";
when 3|13|23|33|43|53=>qsl<="0011";
when 4|14|24|34|44|54=>qsl<="0100";
when 5|15|25|35|45|55=>qsl<="0101";
when 6|16|26|36|46|56=>qsl<="0110";
when 7|17|27|37|47|57=>qsl<="0111";
when 8|18|28|38|48|58=>qsl<="1000";
when 9|19|29|39|49|59=>qsl<="1001";
when others=>null;
end case;
case sec1 is
when 0|1|2|3|4|5|6|7|8|9=>qsh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qsh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qsh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qsh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qsh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qsh<="1001";
when others=>null;
end case;
end process;
process(min1)
begin
case min1 is
when 0|10|20|30|40|50=>qml<="0000";
when 1|11|21|31|41|51=>qml<="0001";
when 2|12|22|32|42|52=>qml<="0010";
when 3|13|23|33|43|53=>qml<="0011";
when 4|14|24|34|44|54=>qml<="0100";
when 5|15|25|35|45|55=>qml<="0101";
when 6|16|26|36|46|56=>qml<="0110";
when 7|17|27|37|47|57=>qml<="0111";
when 8|18|28|38|48|58=>qml<="1000";
when 9|19|29|39|49|59=>qml<="1001";
when others=>null;
end case;
case min1 is
when 0|1|2|3|4|5|6|7|8|9=>qmh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qmh<="0001";
when 20|21|22|23|24|25|26|27|28|29=>qmh<="0010";
when 30|31|32|33|34|35|36|37|38|39=>qmh<="0011";
when 40|41|42|43|44|45|46|47|48|49=>qmh<="0100";
when 50|51|52|53|54|55|56|57|58|59=>qmh<="0101";
when others=>null;
end case;
end process;
process(hour1)
begin
case hour1 is
when 0|10|20=>qhl<="0000";
when 1|11|21=>qhl<="0001";
when 2|12|22=>qhl<="0010";
when 3|13|23=>qhl<="0011";
when 4|14=>qhl<="0100";
when 5|15=>qhl<="0101";
when 6|16=>qhl<="0110";
when 7|17=>qhl<="0111";
when 8|18=>qhl<="1000";
when 9|19=>qhl<="1001";
when others=>null;
end case;
case hour1 is
when 0|1|2|3|4|5|6|7|8|9=>qhh<="0000";
when 10|11|12|13|14|15|16|17|18|19=>qhh<="0001";
when 20|21|22|23=>qhh<="0010";
when others=>null;
end case;
end process;
  回复  更多评论   

# re: VHDL语言数字钟 2009-05-16 17:01 baby

process(clk1khz)
begin
if clk1khz 'event and clk1khz='1' then
if cnt=5 then cnt<=0;
else cnt<=cnt+1;
end if;
end if;
end process;
process(cnt,qhh,qhl,qmh,qml,qsh,qsl,blink)
begin
case cnt is
when 0=>data<=qsl or (blink(0)&blink(0)&blink(0)&blink(0));scan<="000001";
when 1=>data<=qsh or (blink(0)&blink(0)&blink(0)&blink(0));scan<="000010";
when 2=>data<=qml or (blink(1)&blink(1)&blink(1)&blink(1));scan<="000100";
when 3=>data<=qmh or (blink(1)&blink(1)&blink(1)&blink(1));scan<="001000";
when 4=>data<=qhl or (blink(2)&blink(2)&blink(2)&blink(2));scan<="010000";
when 5=>data<=qhh or (blink(2)&blink(2)&blink(2)&blink(2));scan<="100000";
when others=>null;
end case;
end process;
process(data)
begin
case data is
when"0000"=>seg7<="1111110";
when"0001"=>seg7<="0110000";
when"0010"=>seg7<="1101101";
when"0011"=>seg7<="1111001";
when"0100"=>seg7<="0110011";
when"0101"=>seg7<="1011011";
when"0110"=>seg7<="1011111";
when"0111"=>seg7<="1110000";
when"1000"=>seg7<="1111111";
when"1001"=>seg7<="1111011";
when others=>seg7<="0000000";
end case;
end process;
sec<=sec1;
min<=min1;
hour<=hour1;
end;

我的邮箱：sanbudeyu.66@163.com  回复  更多评论   

# re: VHDL语言数字钟[未登录] 2013-06-19 14:23 守护

数字钟控制器：具有时、分、秒计数显示，以24小时循环计时；
LED动态显示时、分、秒；
具有清零、调节小时、分钟、整点报时功能；
每小时整点亮一盏LED，亮30秒熄灭；
每天结束零点蜂鸣灯报警20秒熄灭。  回复  更多评论