为了节省工作量，我打开intel的手册，然后将那些框框里面的字符串复制到一个文本文件里面，最后写一个C++程序用正则表达式处理。流程如下（含代码和文件）：
1、复制格式较混乱的二进制码表。将需要的指令筛选出来之后，可以得到一下文件（完整内容见后面）：
1 14 ib ADC AL,imm8 Add with carry imm8 to AL
2 15 iw ADC AX,imm16 Add with carry imm16 to AX
3 15 id ADC EAX,imm32 Add with carry imm32 to EAX
4 80 /2 ib ADC r/m8,imm8 Add with carry imm8 to r/m8
5 81 /2 iw ADC r/m16,imm16 Add with carry imm16 to r/m16
6 81 /2 id ADC r/m32,imm32 Add with CF imm32 to r/m32
7 83 /2 ib ADC r/m16,imm8 Add with CF sign-extended imm8 to r/m16
8 83 /2 ib ADC r/m32,imm8 Add with CF sign-extended imm8 into r/m32
9 10 /r ADC r/m8,r8 Add with carry byte register to r/m8
10 11 /r ADC r/m16,r16 Add with carry r16 to r/m16
11 11 /r ADC r/m32,r32 Add with CF r32 to r/m32
12 12 /r ADC r8,r/m8 Add with carry r/m8 to byte register
13 13 /r ADC r16,r/m16 Add with carry r/m16 to r16
14 13 /r ADC r32,r/m32 Add with CF r/m32 to r32
2、手工修复一些小问题，譬如intel的某些笔误会让参数imm8写成i mm8，参数后面有星号等等问题。因为这些地方很少，因此手工修复。
3、写C++代码处理：
1 #include "..\..\..\..\VL++\Library\Platform\VL_Console.h"
2 #include "..\..\..\..\VL++\Library\Data\VL_System.h"
3 #include "..\..\..\..\VL++\Library\Data\VL_Stream.h"
4 #include "..\..\..\..\VL++\Library\Data\VL_DataAccess.h"
5 #include "..\..\..\..\VL++\Library\Data\Grammar2\VL_RegTools.h"
6
7 using namespace vl;
8 using namespace vl::platform;
9 using namespace vl::system;
10 using namespace vl::stream;
11 using namespace vl::grammar;
12
13 VUnicodeString FillStr(VUnicodeString String , VInt Length)
14 {
15 while(String.Length()<Length)
16 {
17 String+=L" ";
18 }
19 return String;
20 }
21
22 void GenerateProcessed(VUnicodeString In , VUnicodeString Out)
23 {
24 VL_FileStream FileIn(In,VL_FileStream::vomRead);
25 VL_FileStream FileOut(Out,VL_FileStream::vomWrite);
26 VL_StreamReader Reader(&FileIn,false);
27 VL_StreamWriter Writer(vceUtf16,true,&FileOut,false);
28
29 VUnicodeString BinCode=L"(?:<#BINCODE>[0-9A-F]{2})(\\s(?:<#BINCODE>[0-9A-F]{2}))*(\\+\\s*(?:<#BINCODE_PLUS>i|rb|rw|rd))?";
30 VUnicodeString BinExt=L"(?:<#BINCODE_EXT>\\s(/[0-7]|/r))?(?:<#BINCODE_IMM>\\s(ib|iw|id|cb|cw|cd|cp))?";
31 VUnicodeString Name=L"\\s(?:<#NAME>[A-Z][A-Z0-9]*)";
32 VUnicodeString Param=L"(?:<#PARAM>AX|AL|EAX|CX|CL|ECX|CS|DS|ES|SS|FS|GS|[0-9]+|rel8|rel16|rel32|ptr16:16|ptr16:32|r8|r16|r32|imm8|imm16|imm32|r/m8|r/m16|r/m32|m2byte|m8|m16|m32|m64|m128|m16:16|m16:32|m16&32|m16&16|m32&32|moffs8|moffs16|moffs32|Sreg|m16int|m32int|m64int|m32fp|m64fp|m80fp|m|ST|ST\\(0\\)|ST\\(i\\))";
33 VUnicodeString Comment=L"\\s+(?:<#COMMENT>\\.*)";
34 VUnicodeString Expression=BinCode+BinExt+Name+L"(\\s"+Param+L"(,\\s*"+Param+L")*)?"+Comment;
35 VL_RegExp Regex(Expression,true);
36
37 while(!Reader.IsEnd())
38 {
39 VUnicodeString Line=Reader.ReadLine();
40 if(Line!=L"")
41 {
42 VL_RegExp::ResultPtr MatchResult=Regex.MatchWhole(Line);
43 if(MatchResult->IsMatched())
44 {
45 VInt ParamOffset=0;
46 if(MatchResult->GetStorage(L"COMMENT",0)[0]==L'←')
47 {
48 ParamOffset=1;
49 }
50
51 VUnicodeString BinCode;
52 for(VInt i=0;i<MatchResult->GetStorageCount(L"BINCODE");i++)
53 {
54 BinCode+=MatchResult->GetStorage(L"BINCODE",i);
55 }
56 if(MatchResult->GetStorageCount(L"BINCODE_PLUS")>0)
57 {
58 BinCode+=L"+"+MatchResult->GetStorage(L"BINCODE_PLUS",0);
59 }
60 if(MatchResult->GetStorageCount(L"BINCODE_EXT")>0)
61 {
62 BinCode+=MatchResult->GetStorage(L"BINCODE_EXT",0);
63 }
64 if(MatchResult->GetStorageCount(L"BINCODE_IMM")>0)
65 {
66 BinCode+=MatchResult->GetStorage(L"BINCODE_IMM",0);
67 }
68
69 VUnicodeString Main;
70 Main+=MatchResult->GetStorage(L"NAME",0);
71 for(VInt i=0;i<MatchResult->GetStorageCount(L"PARAM")-ParamOffset;i++)
72 {
73 Main+=+L","+MatchResult->GetStorage(L"PARAM",i);
74 }
75
76 VUnicodeString Comment=MatchResult->GetStorage(L"COMMENT",0);
77 if(ParamOffset)
78 {
79 Comment=MatchResult->GetStorage(L"PARAM",MatchResult->GetStorageCount(L"PARAM")-1)+L" "+Comment;
80 }
81 VUnicodeString NewLine=FillStr(BinCode,20)+FillStr(Main,30)+Comment;
82 Writer.WriteLine(NewLine);
83 }
84 else
85 {
86 GetConsole()->Write(L"[ERROR]"+Line+L"\r\n");
87 }
88 }
89 }
90 }
91
92 void vlmain()
93 {
94 GetConsole()->SetTitle(L"Vczh Library++ 2.0 Assembler");
95 GetConsole()->SetTestMemoryLeaks(true);
96 GetConsole()->SetPauseOnExit(true);
97
98 VUnicodeString WorkData=VFileName(GetConsole()->GetAppPath()).MakeAbsolute(L"..\\..\\TestData\\").GetStrW();
99
100 VUnicodeString Original=WorkData+L"Ins_Original.txt";
101 VUnicodeString Processed=WorkData+L"Ins_Processed.txt";
102 GenerateProcessed(Original,Processed);
103 GetConsole()->Write(L"Stop generating\r\n");
104 }
于是就得到了一个格式完整的文件了。这个文件格式清晰，可以使用更加简单的正则表达式处理。
1 14 ib ADC,AL,imm8 Add with carry imm8 to AL
2 15 iw ADC,AX,imm16 Add with carry imm16 to AX
3 15 id ADC,EAX,imm32 Add with carry imm32 to EAX
4 80 /2 ib ADC,r/m8,imm8 Add with carry imm8 to r/m8
5 81 /2 iw ADC,r/m16,imm16 Add with carry imm16 to r/m16
6 81 /2 id ADC,r/m32,imm32 Add with CF imm32 to r/m32
7 83 /2 ib ADC,r/m16,imm8 Add with CF sign-extended imm8 to r/m16
8 83 /2 ib ADC,r/m32,imm8 Add with CF sign-extended imm8 into r/m32
9 10 /r ADC,r/m8,r8 Add with carry byte register to r/m8
10 11 /r ADC,r/m16,r16 Add with carry r16 to r/m16
11 11 /r ADC,r/m32,r32 Add with CF r32 to r/m32
12 12 /r ADC,r8,r/m8 Add with carry r/m8 to byte register
13 13 /r ADC,r16,r/m16 Add with carry r/m16 to r16
14 13 /r ADC,r32,r/m32 Add with CF r/m32 to r32
最后一步就是将这些东西变成C++的大常数数组，这个就不写出来了。
附筛选出来的格式化的完整内容：
1 14 ib ADC,AL,imm8 Add with carry imm8 to AL
2 15 iw ADC,AX,imm16 Add with carry imm16 to AX
3 15 id ADC,EAX,imm32 Add with carry imm32 to EAX
4 80 /2 ib ADC,r/m8,imm8 Add with carry imm8 to r/m8
5 81 /2 iw ADC,r/m16,imm16 Add with carry imm16 to r/m16
6 81 /2 id ADC,r/m32,imm32 Add with CF imm32 to r/m32
7 83 /2 ib ADC,r/m16,imm8 Add with CF sign-extended imm8 to r/m16
8 83 /2 ib ADC,r/m32,imm8 Add with CF sign-extended imm8 into r/m32
9 10 /r ADC,r/m8,r8 Add with carry byte register to r/m8
10 11 /r ADC,r/m16,r16 Add with carry r16 to r/m16
11 11 /r ADC,r/m32,r32 Add with CF r32 to r/m32
12 12 /r ADC,r8,r/m8 Add with carry r/m8 to byte register
13 13 /r ADC,r16,r/m16 Add with carry r/m16 to r16
14 13 /r ADC,r32,r/m32 Add with CF r/m32 to r32
15 04 ib ADD,AL,imm8 Add imm8 to AL
16 05 iw ADD,AX,imm16 Add imm16 to AX
17 05 id ADD,EAX,imm32 Add imm32 to EAX
18 80 /0 ib ADD,r/m8,imm8 Add imm8 to r/m8
19 81 /0 iw ADD,r/m16,imm16 Add imm16 to r/m16
20 81 /0 id ADD,r/m32,imm32 Add imm32 to r/m32
21 83 /0 ib ADD,r/m16,imm8 Add sign-extended imm8 to r/m16
22 83 /0 ib ADD,r/m32,imm8 Add sign-extended imm8 to r/m32
23 00 /r ADD,r/m8,r8 Add r8 to r/m8
24 01 /r ADD,r/m16,r16 Add r16 to r/m16
25 01 /r ADD,r/m32,r32 Add r32 to r/m32
26 02 /r ADD,r8,r/m8 Add r/m8 to r8
27 03 /r ADD,r16,r/m16 Add r/m16 to r16
28 03 /r ADD,r32,r/m32 Add r/m32 to r32
29 24 ib AND,AL,imm8 AL AND imm8
30 25 iw AND,AX,imm16 AX AND imm16
31 25 id AND,EAX,imm32 EAX AND imm32
32 80 /4 ib AND,r/m8,imm8 r/m8 AND imm8
33 81 /4 iw AND,r/m16,imm16 r/m16 AND imm16
34 81 /4 id AND,r/m32,imm32 r/m32 AND imm32
35 83 /4 ib AND,r/m16,imm8 r/m16 AND imm8 (sign-extended)
36 83 /4 ib AND,r/m32,imm8 r/m32 AND imm8 (sign-extended)
37 20 /r AND,r/m8,r8 r/m8 AND r8
38 21 /r AND,r/m16,r16 r/m16 AND r16
39 21 /r AND,r/m32,r32 r/m32 AND r32
40 22 /r AND,r8,r/m8 r8 AND r/m8
41 23 /r AND,r16,r/m16 r16 AND r/m16
42 23 /r AND,r32,r/m32 r32 AND r/m32
43 62 /r BOUND,r16,m16&16 Check if r16 (array index) is within bounds specified by m16&16
44 62 /r BOUND,r32,m32&32 Check if r32 (array index) is within bounds specified by m32&32
45 0FBC BSF,r16,r/m16 Bit scan forward on r/m16
46 0FBC BSF,r32,r/m32 Bit scan forward on r/m32
47 0FBD BSR,r16,r/m16 Bit scan reverse on r/m16
48 0FBD BSR,r32,r/m32 Bit scan reverse on r/m32
49 0FC8+rd BSWAP,r32 Reverses the byte order of a 32-bit register.
50 0FA3 BT,r/m16,r16 Store selected bit in CF flag
51 0FA3 BT,r/m32,r32 Store selected bit in CF flag
52 0FBA /4 ib BT,r/m16,imm8 Store selected bit in CF flag
53 0FBA /4 ib BT,r/m32,imm8 Store selected bit in CF flag
54 0FBB BTC,r/m16,r16 Store selected bit in CF flag and complement
55 0FBB BTC,r/m32,r32 Store selected bit in CF flag and complement
56 0FBA /7 ib BTC,r/m16,imm8 Store selected bit in CF flag and complement
57 0FBA /7 ib BTC,r/m32,imm8 Store selected bit in CF flag and complement
58 0FB3 BTR,r/m16,r16 Store selected bit in CF flag and clear
59 0FB3 BTR,r/m32,r32 Store selected bit in CF flag and clear
60 0FBA /6 ib BTR,r/m16,imm8 Store selected bit in CF flag and clear
61 0FBA /6 ib BTR,r/m32,imm8 Store selected bit in CF flag and clear
62 0FAB BTS,r/m16,r16 Store selected bit in CF flag and set
63 0FAB BTS,r/m32,r32 Store selected bit in CF flag and set
64 0FBA /5 ib BTS,r/m16,imm8 Store selected bit in CF flag and set
65 0FBA /5 ib BTS,r/m32,imm8 Store selected bit in CF flag and set
66 E8 cw CALL,rel16 Call near, relative, displacement relative to next instruction
67 E8 cd CALL,rel32 Call near, relative, displacement relative to next instruction
68 FF /2 CALL,r/m16 Call near, absolute indirect, address given in r/m16
69 FF /2 CALL,r/m32 Call near, absolute indirect, address given in r/m32
70 9A cd CALL,ptr16:16 Call far, absolute, address given in operand
71 9A cp CALL,ptr16:32 Call far, absolute, address given in operand
72 FF /3 CALL,m16:16 Call far, absolute indirect, address given in m16:16
73 FF /3 CALL,m16:32 Call far, absolute indirect, address given in m16:32
74 98 CBW AX ← sign-extend of AL
75 98 CWDE EAX ← sign-extend of AX
76 F8 CLC Clear CF flag.
77 FC CLD Clear DF flag.
78 FA CLI Clear interrupt flag; interrupts disabled when interrupt flag cleared.
79 F5 CMC Complement CF flag.
80 0F47 /r CMOVA,r16,r/m16 Move if above (CF=0 and ZF=0).
81 0F47 /r CMOVA,r32,r/m32 Move if above (CF=0 and ZF=0).
82 0F43 /r CMOVAE,r16,r/m16 Move if above or equal (CF=0).
83 0F43 /r CMOVAE,r32,r/m32 Move if above or equal (CF=0).
84 0F42 /r CMOVB,r16,r/m16 Move if below (CF=1).
85 0F42 /r CMOVB,r32,r/m32 Move if below (CF=1).
86 0F46 /r CMOVBE,r16,r/m16 Move if below or equal (CF=1 or ZF=1).
87 0F46 /r CMOVBE,r32,r/m32 Move if below or equal (CF=1 or ZF=1).
88 0F42 /r CMOVC,r16,r/m16 Move if carry (CF=1).
89 0F42 /r CMOVC,r32,r/m32 Move if carry (CF=1).
90 0F44 /r CMOVE,r16,r/m16 Move if equal (ZF=1).
91 0F44 /r CMOVE,r32,r/m32 Move if equal (ZF=1).
92 0F4F /r CMOVG,r16,r/m16 Move if greater (ZF=0 and SF=OF).
93 0F4F /r CMOVG,r32,r/m32 Move if greater (ZF=0 and SF=OF).
94 0F4D /r CMOVGE,r16,r/m16 Move if greater or equal (SF=OF).
95 0F4D /r CMOVGE,r32,r/m32 Move if greater or equal (SF=OF).
96 0F4C /r CMOVL,r16,r/m16 Move if less (SF<>OF).
97 0F4C /r CMOVL,r32,r/m32 Move if less (SF<>OF).
98 0F4E /r CMOVLE,r16,r/m16 Move if less or equal (ZF=1 or SF<>OF).
99 0F4E /r CMOVLE,r32,r/m32 Move if less or equal (ZF=1 or SF<>OF).
100 0F46 /r CMOVNA,r16,r/m16 Move if not above (CF=1 or ZF=1).
101 0F46 /r CMOVNA,r32,r/m32 Move if not above (CF=1 or ZF=1).
102 0F42 /r CMOVNAE,r16,r/m16 Move if not above or equal (CF=1).
103 0F42 /r CMOVNAE,r32,r/m32 Move if not above or equal (CF=1).
104 0F43 /r CMOVNB,r16,r/m16 Move if not below (CF=0).
105 0F43 /r CMOVNB,r32,r/m32 Move if not below (CF=0).
106 0F47 /r CMOVNBE,r16,r/m16 Move if not below or equal (CF=0 and ZF=0).
107 0F47 /r CMOVNBE,r32,r/m32 Move if not below or equal (CF=0 and ZF=0).
108 0F43 /r CMOVNC,r16,r/m16 Move if not carry (CF=0).
109 0F43 /r CMOVNC,r32,r/m32 Move if not carry (CF=0).
110 0F45 /r CMOVNE,r16,r/m16 Move if not equal (ZF=0).
111 0F45 /r CMOVNE,r32,r/m32 Move if not equal (ZF=0).
112 0F4E /r CMOVNG,r16,r/m16 Move if not greater (ZF=1 or SF<>OF).
113 0F4E /r CMOVNG,r32,r/m32 Move if not greater (ZF=1 or SF<>OF).
114 0F4C /r CMOVNGE,r16,r/m16 Move if not greater or equal (SF<>OF.)
115 0F4C /r CMOVNGE,r32,r/m32 Move if not greater or equal (SF<>OF).
116 0F4D /r CMOVNL,r16,r/m16 Move if not less (SF=OF).
117 0F4D /r CMOVNL,r32,r/m32 Move if not less (SF=OF).
118 0F4F /r CMOVNLE,r16,r/m16 Move if not less or equal (ZF=0 and SF=OF).
119 0F4F /r CMOVNLE,r32,r/m32 Move if not less or equal (ZF=0 and SF=OF).
120 3C ib CMP,AL,imm8 Compare imm8 with AL.
121 3D iw CMP,AX,imm16 Compare imm16 with AX.
122 3D id CMP,EAX,imm32 Compare imm32 with EAX.
123 80 /7 ib CMP,r/m8,imm8 Compare imm8 with r/m8.
124 81 /7 iw CMP,r/m16,imm16 Compare imm16 with r/m16.
125 81 /7 id CMP,r/m32,imm32 Compare imm32 with r/m32.
126 83 /7 ib CMP,r/m16,imm8 Compare imm8 with r/m16.
127 83 /7 ib CMP,r/m32,imm8 Compare imm8 with r/m32.
128 38 /r CMP,r/m8,r8 Compare r8 with r/m8.
129 39 /r CMP,r/m16,r16 Compare r16 with r/m16.
130 39 /r CMP,r/m32,r32 Compare r32 with r/m32.
131 3A /r CMP,r8,r/m8 Compare r/m8 with r8.
132 3B /r CMP,r16,r/m16 Compare r/m16 with r16.
133 3B /r CMP,r32,r/m32 Compare r/m32 with r32.
134 A6 CMPSB Compares byte at address DS:(E)SI with byte at address ES:(E)DI and sets the status flags accordingly.
135 A7 CMPSW Compares word at address DS:(E)SI with word at address ES:(E)DI and sets the status flags accordingly.
136 A7 CMPSD Compares doubleword at address DS:(E)SI with doubleword at address ES:(E)DI and sets the status flags accordingly.
137 99 CWD DX:AX ← sign-extend of AX
138 99 CDQ EDX:EAX ← sign-extend of EAX
139 FE /1 DEC,r/m8 Decrement r/m8 by 1.
140 FF /1 DEC,r/m16 Decrement r/m16 by 1.
141 FF /1 DEC,r/m32 Decrement r/m32 by 1.
142 48+rw DEC,r16 Decrement r16 by 1.
143 48+rd DEC,r32 Decrement r32 by 1.
144 F6 /6 DIV,r/m8 Unsigned divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
145 F7 /6 DIV,r/m16 Unsigned divide DX:AX by r/m16, with result stored in AX ← Quotient, DX ← Remainder.
146 F7 /6 DIV,r/m32 Unsigned divide EDX:EAX by r/m32, with result stored in EAX ← Quotient, EDX ← Remainder.
147 D9E1 FABS Replace ST with its absolute value.
148 D8 /0 FADD,m32fp Add m32fp to ST(0) and store result in ST(0).
149 DC /0 FADD,m64fp Add m64fp to ST(0) and store result in ST(0).
150 D8C0+i FADD,ST(0),ST(i) Add ST(0) to ST(i) and store result in ST(0).
151 DCC0+i FADD,ST(i),ST(0) Add ST(i) to ST(0) and store result in ST(i).
152 DEC0+i FADDP,ST(i),ST(0) Add ST(0) to ST(i), store result in ST(i), and pop the register stack.
153 DEC1 FADDP Add ST(0) to ST(1), store result in ST(1), and pop the register stack.
154 DA /0 FIADD,m32int Add m32int to ST(0) and store result in ST(0).
155 DE /0 FIADD,m16int Add m16int to ST(0) and store result in ST(0).
156 D9E0 FCHS Complements sign of ST(0)
157 DAC0+i FCMOVB,ST(0),ST(i) Move if below (CF=1).
158 DAC8+i FCMOVE,ST(0),ST(i) Move if equal (ZF=1).
159 DAD0+i FCMOVBE,ST(0),ST(i) Move if below or equal (CF=1 or ZF=1).
160 DAD8+i FCMOVU,ST(0),ST(i) Move if unordered (PF=1).
161 DBC0+i FCMOVNB,ST(0),ST(i) Move if not below (CF=0).
162 DBC8+i FCMOVNE,ST(0),ST(i) Move if not equal (ZF=0).
163 DBD0+i FCMOVNBE,ST(0),ST(i) Move if not below or equal (CF=0 and ZF=0).
164 DBD8+i FCMOVNU,ST(0),ST(i) Move if not unordered (PF=0).
165 D8 /2 FCOM,m32fp Compare ST(0) with m32fp.
166 DC /2 FCOM,m64fp Compare ST(0) with m64fp.
167 D8D0+i FCOM,ST(i) Compare ST(0) with ST(i).
168 D8D1 FCOM Compare ST(0) with ST(1).
169 D8 /3 FCOMP,m32fp Compare ST(0) with m32fp and pop register stack.
170 DC /3 FCOMP,m64fp Compare ST(0) with m64fp and pop register stack.
171 D8D8+i FCOMP,ST(i) Compare ST(0) with ST(i) and pop register stack.
172 D8D9 FCOMP Compare ST(0) with ST(1) and pop register stack.
173 DED9 FCOMPP Compare ST(0) with ST(1) and pop register stack twice.
174 DBF0+i FCOMI,ST,ST(i) Compare ST(0) with ST(i) and set status flags accordingly.
175 DFF0+i FCOMIP,ST,ST(i) Compare ST(0) with ST(i), set status flags accordingly, and pop register stack.
176 DBE8+i FUCOMI,ST,ST(i) Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly.
177 DFE8+i FUCOMIP,ST,ST(i) Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack.
178 D9FF FCOS Replace ST(0) with its cosine.
179 D9F6 FDECSTP Decrement TOP field in FPU status word.
180 D8 /6 FDIV,m32fp Divide ST(0) by m32fp and store result in ST(0).
181 DC /6 FDIV,m64fp Divide ST(0) by m64fp and store result in ST(0).
182 D8F0+i FDIV,ST(0),ST(i) Divide ST(0) by ST(i) and store result in ST(0).
183 DCF8+i FDIV,ST(i),ST(0) Divide ST(i) by ST(0) and store result in ST(i).
184 DEF8+i FDIVP,ST(i),ST(0) Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
185 DEF9 FDIVP Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
186 DA /6 FIDIV,m32int Divide ST(0) by m32int and store result in ST(0).
187 DE /6 FIDIV,m16int Divide ST(0) by m64int and store result in ST(0).
188 D8 /7 FDIVR,m32fp Divide m32fp by ST(0) and store result in ST(0)
189 DC /7 FDIVR,m64fp Divide m64fp by ST(0) and store result in ST(0)
190 D8F8+i FDIVR,ST(0),ST(i) Divide ST(i) by ST(0) and store result in ST(0)
191 DCF0+i FDIVR,ST(i),ST(0) Divide ST(0) by ST(i) and store result in ST(i)
192 DEF0+i FDIVRP,ST(i),ST(0) Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
193 DEF1 FDIVRP Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
194 DA /7 FIDIVR,m32int Divide m32int by ST(0) and store result in ST(0)
195 DE /7 FIDIVR,m16int Divide m16int by ST(0) and store result in ST(0)
196 DE /2 FICOM,m16int Compare ST(0) with m16int.
197 DA /2 FICOM,m32int Compare ST(0) with m32int.
198 DE /3 FICOMP,m16int Compare ST(0) with m16int and pop stack register.
199 DA /3 FICOMP,m32int Compare ST(0) with m32int and pop stack register.
200 DF /0 FILD,m16int Push m16int onto the FPU register stack.
201 DB /0 FILD,m32int Push m32int onto the FPU register stack.
202 DF /5 FILD,m64int Push m64int onto the FPU register stack.
203 D9F7 FINCSTP Increment the TOP field in the FPU status register.
204 DF /2 FIST,m16int Store ST(0) in m16int.
205 DB /2 FIST,m32int Store ST(0) in m32int.
206 DF /3 FISTP,m16int Store ST(0) in m16int and pop register stack.
207 DB /3 FISTP,m32int Store ST(0) in m32int and pop register stack.
208 DF /7 FISTP,m64int Store ST(0) in m64int and pop register stack.
209 DF /1 FISTTP,m16int Store ST as a signed integer (truncate) inm16int and pop ST.
210 DB /1 FISTTP,m32int Store ST as a signed integer (truncate) inm32int and pop ST.
211 DD /1 FISTTP,m64int Store ST as a signed integer(truncate) inm64int and pop ST.
212 D9 /0 FLD,m32fp Push m32fp onto the FPU register stack.
213 DD /0 FLD,m64fp Push m64fp onto the FPU register stack.
214 DB /5 FLD,m80fp Push m80fp onto the FPU register stack.
215 D9C0+i FLD,ST(i) Push ST(i) onto the FPU register stack.
216 D9E8 FLD1 Push +1.0 onto the FPU register stack.
217 D9E9 FLDL2T Push log210 onto the FPU register stack.
218 D9EA FLDL2E Push log2e onto the FPU register stack.
219 D9EB FLDPI Push π onto the FPU register stack.
220 D9EC FLDLG2 Push log102 onto the FPU register stack.
221 D9ED FLDLN2 Push loge2 onto the FPU register stack.
222 D9EE FLDZ Push +0.0 onto the FPU register stack.
223 D8 /1 FMUL,m32fp Multiply ST(0) by m32fp and store result in ST(0)
224 DC /1 FMUL,m64fp Multiply ST(0) by m64fp and store result in ST(0)
225 D8C8+i FMUL,ST(0),ST(i) Multiply ST(0) by ST(i) and store result in ST(0)
226 DCC8+i FMUL,ST(i),ST(0) Multiply ST(i) by ST(0) and store result in ST(i)
227 DEC8+i FMULP,ST(i),ST(0) Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack
228 DEC9 FMULP Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack
229 DA /1 FIMUL,m32int Multiply ST(0) by m32int and store result in ST(0)
230 DE /1 FIMUL,m16int Multiply ST(0) by m16int and store result in ST(0)
231 D9F3 FPATAN Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack.
232 D9FC FRNDINT Round ST(0) to an integer.
233 D9FD FSCALE Scale ST(0) by ST(1).
234 D9FE FSIN Replace ST(0) with its sine.
235 D9FB FSINCOS Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack.
236 D9FA FSQRT Computes square root of ST(0) and stores the result in ST(0).
237 D9 /2 FST,m32fp Copy ST(0) to m32fp.
238 DD /2 FST,m64fp Copy ST(0) to m64fp.
239 DDD0+i FST,ST(i) Copy ST(0) to ST(i).
240 D9 /3 FSTP,m32fp Copy ST(0) to m32fp and pop register stack.
241 DD /3 FSTP,m64fp Copy ST(0) to m64fp and pop register stack.
242 DB /7 FSTP,m80fp Copy ST(0) to m80fp and pop register stack.
243 DDD8+i FSTP,ST(i) Copy ST(0) to ST(i) and pop register stack.
244 9BDD /7 FSTSW,m2byte Store FPU status word at m2byte after checking forpending unmasked floating-point exceptions.
245 9BDFE0 FSTSW,AX Store FPU status word in AX register after checking forpending unmasked floating-point exceptions.
246 DD /7 FNSTSW,m2byte Store FPU status word at m2byte without checking forpending unmasked floating-point exceptions.
247 DFE0 FNSTSW,AX Store FPU status word in AX register without checking forpending unmasked floating-point exceptions.
248 D8 /4 FSUB,m32fp Subtract m32fp from ST(0) and store result in ST(0).
249 DC /4 FSUB,m64fp Subtract m64fp from ST(0) and store result in ST(0).
250 D8E0+i FSUB,ST(0),ST(i) Subtract ST(i) from ST(0) and store result in ST(0).
251 DCE8+i FSUB,ST(i),ST(0) Subtract ST(0) from ST(i) and store result in ST(i).
252 DEE8+i FSUBP,ST(i),ST(0) Subtract ST(0) from ST(i), store result in ST(i), and pop register stack.
253 DEE9 FSUBP Subtract ST(0) from ST(1), store result in ST(1), and pop register stack.
254 DA /4 FISUB,m32int Subtract m32int from ST(0) and store result in ST(0).
255 DE /4 FISUB,m16int Subtract m16int from ST(0) and store result in ST(0).
256 D8 /5 FSUBR,m32fp Subtract ST(0) from m32fp and store result in ST(0).
257 DC /5 FSUBR,m64fp Subtract ST(0) from m64fp and store result in ST(0).
258 D8E8+i FSUBR,ST(0),ST(i) Subtract ST(0) from ST(i) and store result in ST(0).
259 DCE0+i FSUBR,ST(i),ST(0) Subtract ST(i) from ST(0) and store result in ST(i).
260 DEE0+i FSUBRP,ST(i),ST(0) Subtract ST(i) from ST(0), store result in ST(i), and pop register stack.
261 DEE1 FSUBRP Subtract ST(1) from ST(0), store result in ST(1), and pop register stack.
262 DA /5 FISUBR,m32int Subtract ST(0) from m32int and store result in ST(0).
263 DE /5 FISUBR,m16int Subtract ST(0) from m16int and store result in ST(0).
264 D9E4 FTST Compare ST(0) with 0.0.
265 DDE0+i FUCOM,ST(i) Compare ST(0) with ST(i).
266 DDE1 FUCOM Compare ST(0) with ST(1).
267 DDE8+i FUCOMP,ST(i) Compare ST(0) with ST(i) and pop register stack.
268 DDE9 FUCOMP Compare ST(0) with ST(1) and pop register stack.
269 DAE9 FUCOMPP Compare ST(0) with ST(1) and pop register stack twice.
270 D9E5 FXAM Classify value or number in ST(0).
271 D9C8+i FXCH,ST(i) Exchange the contents of ST(0) and ST(i).
272 D9C9 FXCH Exchange the contents of ST(0) and ST(1).
273 D9F1 FYL2X Replace ST(1)with (ST(1) * log2ST(0)) and pop the register stack.
274 D9F9 FYL2XP1 Replace ST(1) with ST(1) * log2(ST(0) + 1.0) and pop the register stack.
275 F6 /7 IDIV,r/m8 Signed divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
276 F7 /7 IDIV,r/m16 Signed divide DX:AX by r/m16, with result stored in AX ← Quotient, DX ← Remainder.
277 F7 /7 IDIV,r/m32 Signed divide EDX:EAX by r/m32, with result stored in EAX ← Quotient, EDX ← Remainder.
278 F6 /5 IMUL,r/m8 AX← AL * r/m byte.
279 F7 /5 IMUL,r/m16 DX:AX ← AX * r/m word.
280 F7 /5 IMUL,r/m32 EDX:EAX ← EAX * r/m doubleword.
281 0FAF /r IMUL,r16,r/m16 word register ← word register * r/m word.
282 0FAF /r IMUL,r32,r/m32 doubleword register ← doubleword register * r/m doubleword.
283 6B /r ib IMUL,r16,r/m16,imm8 word register ← r/m16 * sign-extended immediate byte.
284 6B /r ib IMUL,r32,r/m32,imm8 doubleword register ← r/m32 * sign-extended immediate byte.
285 6B /r ib IMUL,r16,imm8 word register ← word register * sign-extended immediate byte.
286 6B /r ib IMUL,r32,imm8 doubleword register ← doubleword register * signextended immediate byte.
287 69 /r iw IMUL,r16,r/m16,imm16 word register ← r/m16 * immediate word.
288 69 /r id IMUL,r32,r/m32,imm32 doubleword register ← r/m32 * immediate doubleword.
289 69 /r iw IMUL,r16,imm16 word register ← r/m16 * immediate word.
290 69 /r id IMUL,r32,imm32 doubleword register ← r/m32 * immediate doubleword.
291 FE /0 INC,r/m8 Increment r/m byte by 1.
292 FF /0 INC,r/m16 Increment r/m word by 1.
293 FF /0 INC,r/m32 Increment r/m doubleword by 1.
294 40+rw INC,r16 Increment word register by 1.
295 40+rd INC,r32 Increment doubleword register by 1.
296 CC INT,3 Interrupt 3—trap to debugger.
297 CD ib INT,imm8 Interrupt vector number specified by immediate byte.
298 CE INTO Interrupt 4—if overflow flag is 1.
299 77 cb JA,rel8 Jump short if above (CF=0 and ZF=0).
300 73 cb JAE,rel8 Jump short if above or equal (CF=0).
301 72 cb JB,rel8 Jump short if below (CF=1).
302 76 cb JBE,rel8 Jump short if below or equal (CF=1 or ZF=1).
303 72 cb JC,rel8 Jump short if carry (CF=1).
304 E3 cb JCXZ,rel8 Jump short if CX register is 0.
305 E3 cb JECXZ,rel8 Jump short if ECX register is 0.
306 74 cb JE,rel8 Jump short if equal (ZF=1).
307 7F cb JG,rel8 Jump short if greater (ZF=0 and SF=OF).
308 7D cb JGE,rel8 Jump short if greater or equal (SF=OF).
309 7C cb JL,rel8 Jump short if less (SF<>OF).
310 7E cb JLE,rel8 Jump short if less or equal (ZF=1 or SF<>OF).
311 76 cb JNA,rel8 Jump short if not above (CF=1 or ZF=1).
312 72 cb JNAE,rel8 Jump short if not above or equal (CF=1).
313 73 cb JNB,rel8 Jump short if not below (CF=0).
314 77 cb JNBE,rel8 Jump short if not below or equal (CF=0 and ZF=0).
315 73 cb JNC,rel8 Jump short if not carry (CF=0).
316 75 cb JNE,rel8 Jump short if not equal (ZF=0).
317 7E cb JNG,rel8 Jump short if not greater (ZF=1 or SF<>OF).
318 7C cb JNGE,rel8 Jump short if not greater or equal (SF<>OF).
319 7D cb JNL,rel8 Jump short if not less (SF=OF).
320 7F cb JNLE,rel8 Jump short if not less or equal (ZF=0 and SF=OF).
321 71 cb JNO,rel8 Jump short if not overflow (OF=0).
322 7B cb JNP,rel8 Jump short if not parity (PF=0).
323 79 cb JNS,rel8 Jump short if not sign (SF=0).
324 75 cb JNZ,rel8 Jump short if not zero (ZF=0).
325 70 cb JO,rel8 Jump short if overflow (OF=1).
326 7A cb JP,rel8 Jump short if parity (PF=1).
327 7A cb JPE,rel8 Jump short if parity even (PF=1).
328 7B cb JPO,rel8 Jump short if parity odd (PF=0).
329 78 cb JS,rel8 Jump short if sign (SF=1).
330 74 cb JZ,rel8 Jump short if zero (ZF = 1).
331 0F87 cw JA,rel16 Jump near if above (CF=0 and ZF=0).
332 0F83 cw JAE,rel16 Jump near if above or equal (CF=0).
333 0F82 cw JB,rel16 Jump near if below (CF=1).
334 0F86 cw JBE,rel16 Jump near if below or equal (CF=1 or ZF=1).
335 0F82 cw JC,rel16 Jump near if carry (CF=1).
336 0F84 cw JE,rel16 Jump near if equal (ZF=1).
337 0F84 cw JZ,rel16 Jump near if 0 (ZF=1).
338 0F8F cw JG,rel16 Jump near if greater (ZF=0 and SF=OF).
339 0F87 cd JA,rel32 Jump near if above (CF=0 and ZF=0).
340 0F83 cd JAE,rel32 Jump near if above or equal (CF=0).
341 0F82 cd JB,rel32 Jump near if below (CF=1).
342 0F86 cd JBE,rel32 Jump near if below or equal (CF=1 or ZF=1).
343 0F82 cd JC,rel32 Jump near if carry (CF=1).
344 0F84 cd JE,rel32 Jump near if equal (ZF=1).
345 0F84 cd JZ,rel32 Jump near if 0 (ZF=1).
346 0F8F cd JG,rel32 Jump near if greater (ZF=0 and SF=OF).
347 EB cb JMP,rel8 Jump short, relative, displacement relative to next instruction.
348 E9 cw JMP,rel16 Jump near, relative, displacement relative to next instruction.
349 E9 cd JMP,rel32 Jump near, relative, displacement relative to next instruction.
350 FF /4 JMP,r/m16 Jump near, absolute indirect, address given in r/m16.
351 FF /4 JMP,r/m32 Jump near, absolute indirect, address given in r/m32.
352 EA cd JMP,ptr16:16 Jump far, absolute, address given in operand.
353 EA cp JMP,ptr16:32 Jump far, absolute, address given in operand.
354 FF /5 JMP,m16:16 Jump far, absolute indirect, address given in m16:16.
355 FF /5 JMP,m16:32 Jump far, absolute indirect, address given in m16:32.
356 8D /r LEA,r16,m Store effective address for m in register r16.
357 8D /r LEA,r32,m Store effective address for m in register r32.
358 AC LODSB Load byte at address DS:(E)SI into AL.
359 AD LODSW Load word at address DS:(E)SI into AX.
360 AD LODSD Load doubleword at address DS:(E)SI into EAX.
361 E2 cb LOOP,rel8 Decrement count; jump short if count ≠ 0.
362 E1 cb LOOPE,rel8 Decrement count; jump short if count ≠ 0 and ZF=1.
363 E1 cb LOOPZ,rel8 Decrement count; jump short if count ≠ 0 and ZF=1.
364 E0 cb LOOPNE,rel8 Decrement count; jump short if count ≠ 0 and ZF=0.
365 E0 cb LOOPNZ,rel8 Decrement count; jump short if count ≠ 0 and ZF=0.
366 88 /r MOV,r/m8,r8 Move r8 to r/m8.
367 89 /r MOV,r/m16,r16 Move r16 to r/m16.
368 89 /r MOV,r/m32,r32 Move r32 to r/m32.
369 8A /r MOV,r8,r/m8 Move r/m8 to r8.
370 8B /r MOV,r16,r/m16 Move r/m16 to r16.
371 8B /r MOV,r32,r/m32 Move r/m32 to r32.
372 8C /r MOV,r/m16,Sreg Move segment register to r/m16.
373 8E /r MOV,Sreg,r/m16 Move r/m16 to segment register.
374 A0 MOV,AL,moffs8 Move byte at (seg:offset) to AL.
375 A1 MOV,AX,moffs16 Move word at (seg:offset) to AX.
376 A1 MOV,EAX,moffs32 Move doubleword at (seg:offset) to EAX.
377 A2 MOV,moffs8,AL Move AL to (seg:offset).
378 A3 MOV,moffs16,AX Move AX to (seg:offset).
379 A3 MOV,moffs32,EAX Move EAX to (seg:offset).
380 B0+rb MOV,r8,imm8 Move imm8 to r8.
381 B8+rw MOV,r16,imm16 Move imm16 to r16.
382 B8+rd MOV,r32,imm32 Move imm32 to r32.
383 C6 /0 MOV,r/m8,imm8 Move imm8 to r/m8.
384 C7 /0 MOV,r/m16,imm16 Move imm16 to r/m16.
385 C7 /0 MOV,r/m32,imm32 Move imm32 to r/m32.
386 A4 MOVSB Move byte at address DS:(E)SI to address ES:(E)DI.
387 A5 MOVSW Move word at address DS:(E)SI to address ES:(E)DI.
388 A5 MOVSD Move doubleword at address DS:(E)SI to address ES:(E)DI.
389 0FB6 /r MOVZX,r16,r/m8 Move byte to word with zero-extension.
390 0FB6 /r MOVZX,r32,r/m8 Move byte to doubleword, zero-extension.
391 0FB7 /r MOVZX,r32,r/m16 Move word to doubleword, zero-extension.
392 F6 /4 MUL,r/m8 Unsigned multiply (AX ← AL * r/m8).
393 F7 /4 MUL,r/m16 Unsigned multiply (DX:AX ← AX * r/m16).
394 F7 /4 MUL,r/m32 Unsigned multiply (EDX:EAX ← EAX * r/m32).
395 F6 /3 NEG,r/m8 Two's complement negate r/m8.
396 F7 /3 NEG,r/m16 Two's complement negate r/m16.
397 F7 /3 NEG,r/m32 Two's complement negate r/m32.
398 F6 /2 NOT,r/m8 Reverse each bit of r/m8.
399 F7 /2 NOT,r/m16 Reverse each bit of r/m16.
400 F7 /2 NOT,r/m32 Reverse each bit of r/m32.
401 0C ib OR,AL,imm8 AL OR imm8.
402 0D iw OR,AX,imm16 AX OR imm16.
403 0D id OR,EAX,imm32 EAX OR imm32.
404 80 /1 ib OR,r/m8,imm8 r/m8 OR imm8.
405 81 /1 iw OR,r/m16,imm16 r/m16 OR imm16.
406 81 /1 id OR,r/m32,imm32 r/m32 OR imm32
407 83 /1 ib OR,r/m16,imm8 r/m16 OR imm8 (sign-extended).
408 83 /1 ib OR,r/m32,imm8 r/m32 OR imm8 (sign-extended).
409 08 /r OR,r/m8,r8 r/m8 OR r8.
410 09 /r OR,r/m16,r16 r/m16 OR r16.
411 09 /r OR,r/m32,r32 r/m32 OR r32.
412 0A /r OR,r8,r/m8 r8 OR r/m8.
413 0B /r OR,r16,r/m16 r16 OR r/m16.
414 0B /r OR,r32,r/m32 r32 OR r/m32.
415 8F /0 POP,r/m16 Pop top of stack into m16; increment stack pointer.
416 8F /0 POP,r/m32 Pop top of stack into m32; increment stack pointer.
417 58+rw POP,r16 Pop top of stack into r16; increment stack pointer.
418 58+rd POP,r32 Pop top of stack into r32; increment stack pointer.
419 1F POP,DS Pop top of stack into DS; increment stack pointer.
420 07 POP,ES Pop top of stack into ES; increment stack pointer.
421 17 POP,SS Pop top of stack into SS; increment stack pointer.
422 0FA1 POP,FS Pop top of stack into FS; increment stack pointer.
423 0FA9 POP,GS Pop top of stack into GS; increment stack pointer.
424 61 POPA Pop DI, SI, BP, BX, DX, CX, and AX.
425 61 POPAD Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
426 FF /6 PUSH,r/m16 Push r/m16.
427 FF /6 PUSH,r/m32 Push r/m32.
428 50+rw PUSH,r16 Push r16.
429 50+rd PUSH,r32 Push r32.
430 6A PUSH,imm8 Push imm8.
431 68 PUSH,imm16 Push imm16.
432 68 PUSH,imm32 Push imm32.
433 0E PUSH,CS Push CS.
434 16 PUSH,SS Push SS.
435 1E PUSH,DS Push DS.
436 06 PUSH,ES Push ES.
437 0FA0 PUSH,FS Push FS.
438 0FA8 PUSH,GS Push GS.
439 60 PUSHA Push AX, CX, DX, BX, original SP, BP, SI, and DI.
440 60 PUSHAD Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.
441 D0 /2 RCL,r/m8,1 Rotate 9 bits (CF, r/m8) left once.
442 D2 /2 RCL,r/m8,CL Rotate 9 bits (CF, r/m8) left CL times.
443 C0 /2 ib RCL,r/m8,imm8 Rotate 9 bits (CF, r/m8) left imm8 times.
444 D1 /2 RCL,r/m16,1 Rotate 17 bits (CF, r/m16) left once.
445 D3 /2 RCL,r/m16,CL Rotate 17 bits (CF, r/m16) left CL times.
446 C1 /2 ib RCL,r/m16,imm8 Rotate 17 bits (CF, r/m16) left imm8 times.
447 D1 /2 RCL,r/m32,1 Rotate 33 bits (CF, r/m32) left once.
448 D3 /2 RCL,r/m32,CL Rotate 33 bits (CF, r/m32) left CL times.
449 C1 /2 ib RCL,r/m32,imm8 Rotate 33 bits (CF, r/m32) left imm8 times.
450 D0 /3 RCR,r/m8,1 Rotate 9 bits (CF, r/m8) right once.
451 D2 /3 RCR,r/m8,CL Rotate 9 bits (CF, r/m8) right CL times.
452 C0 /3 ib RCR,r/m8,imm8 Rotate 9 bits (CF, r/m8) right imm8 times.
453 D1 /3 RCR,r/m16,1 Rotate 17 bits (CF, r/m16) right once.
454 D3 /3 RCR,r/m16,CL Rotate 17 bits (CF, r/m16) right CL times.
455 C1 /3 ib RCR,r/m16,imm8 Rotate 17 bits (CF, r/m16) right imm8 times.
456 D1 /3 RCR,r/m32,1 Rotate 33 bits (CF, r/m32) right once.
457 D3 /3 RCR,r/m32,CL Rotate 33 bits (CF, r/m32) right CL times.
458 C1 /3 ib RCR,r/m32,imm8 Rotate 33 bits (CF, r/m32) right imm8 times.
459 D0 /0 ROL,r/m8,1 Rotate 8 bits r/m8 left once.
460 D2 /0 ROL,r/m8,CL Rotate 8 bits r/m8 left CL times.
461 C0 /0 ib ROL,r/m8,imm8 Rotate 8 bits r/m8 left imm8 times.
462 D1 /0 ROL,r/m16,1 Rotate 16 bits r/m16 left once.
463 D3 /0 ROL,r/m16,CL Rotate 16 bits r/m16 left CL times.
464 C1 /0 ib ROL,r/m16,imm8 Rotate 16 bits r/m16 left imm8 times.
465 D1 /0 ROL,r/m32,1 Rotate 32 bits r/m32 left once.
466 D3 /0 ROL,r/m32,CL Rotate 32 bits r/m32 left CL times.
467 C1 /0 ib ROL,r/m32,imm8 Rotate 32 bits r/m32 left imm8 times.
468 D0 /1 ROR,r/m8,1 Rotate 8 bits r/m8 right once.
469 D2 /1 ROR,r/m8,CL Rotate 8 bits r/m8 right CL times.
470 C0 /1 ib ROR,r/m8,imm8 Rotate 8 bits r/m16 right imm8 times.
471 D1 /1 ROR,r/m16,1 Rotate 16 bits r/m16 right once.
472 D3 /1 ROR,r/m16,CL Rotate 16 bits r/m16 right CL times.
473 C1 /1 ib ROR,r/m16,imm8 Rotate 16 bits r/m16 right imm8 times.
474 D1 /1 ROR,r/m32,1 Rotate 32 bits r/m32 right once.
475 D3 /1 ROR,r/m32,CL Rotate 32 bits r/m32 right CL times.
476 C1 /1 ib ROR,r/m32,imm8 Rotate 32 bits r/m32 right imm8 times.
477 C3 RET Near return to calling procedure.
478 CB RET Far return to calling procedure.
479 C2 iw RET,imm16 Near return to calling procedure and pop imm16 bytes from stack.
480 CA iw RET,imm16 Far return to calling procedure and pop imm16 bytes from stack.
481 9E SAHF Load SF, ZF, AF, PF, and CF from AH into EFLAGS register.
482 D0 /4 SAL,r/m8 Multiply r/m8 by 2, 1 time.
483 D2 /4 SAL,r/m8,CL Multiply r/m8 by 2, CL times.
484 C0 /4 ib SAL,r/m8,imm8 Multiply r/m8 by 2, imm8 times.
485 D1 /4 SAL,r/m16 Multiply r/m16 by 2, 1 time.
486 D3 /4 SAL,r/m16,CL Multiply r/m16 by 2, CL times.
487 C1 /4 ib SAL,r/m16,imm8 Multiply r/m16 by 2, imm8 times.
488 D1 /4 SAL,r/m32 Multiply r/m32 by 2, 1 time.
489 D3 /4 SAL,r/m32,CL Multiply r/m32 by 2, CL times.
490 C1 /4 ib SAL,r/m32,imm8 Multiply r/m32 by 2, imm8 times.
491 D0 /7 SAR,r/m8 Signed divide* r/m8 by 2, 1 times.
492 D2 /7 SAR,r/m8,CL Signed divide* r/m8 by 2, CL times.
493 C0 /7 ib SAR,r/m8,imm8 Signed divide* r/m8 by 2, imm8 times.
494 D1 /7 SAR,r/m16 Signed divide* r/m16 by 2, 1 time.
495 D3 /7 SAR,r/m16,CL Signed divide* r/m16 by 2, CL times.
496 C1 /7 ib SAR,r/m16,imm8 Signed divide* r/m16 by 2, imm8 times.
497 D1 /7 SAR,r/m32 Signed divide* r/m32 by 2, 1 time.
498 D3 /7 SAR,r/m32,CL Signed divide* r/m32 by 2, CL times.
499 C1 /7 ib SAR,r/m32,imm8 Signed divide* r/m32 by 2, imm8 times.
500 D0 /4 SHL,r/m8 Multiply r/m8 by 2, 1 time.
501 D2 /4 SHL,r/m8,CL Multiply r/m8 by 2, CL times.
502 C0 /4 ib SHL,r/m8,imm8 Multiply r/m8 by 2, imm8 times.
503 D1 /4 SHL,r/m16 Multiply r/m16 by 2, 1 time.
504 D3 /4 SHL,r/m16,CL Multiply r/m16 by 2, CL times.
505 C1 /4 ib SHL,r/m16,imm8 Multiply r/m16 by 2, imm8 times.
506 D1 /4 SHL,r/m32 Multiply r/m32 by 2, 1 time.
507 D3 /4 SHL,r/m32,CL Multiply r/m32 by 2, CL times.
508 C1 /4 ib SHL,r/m32,imm8 Multiply r/m32 by 2, imm8 times.
509 D0 /5 SHR,r/m8 Unsigned divide r/m8 by 2, 1 time.
510 D2 /5 SHR,r/m8,CL Unsigned divide r/m8 by 2, CL times.
511 C0 /5 ib SHR,r/m8,imm8 Unsigned divide r/m8 by 2, imm8 times.
512 D1 /5 SHR,r/m16 Unsigned divide r/m16 by 2, 1 time.
513 D3 /5 SHR,r/m16,CL Unsigned divide r/m16 by 2, CL times.
514 C1 /5 ib SHR,r/m16,imm8 Unsigned divide r/m16 by 2, imm8 times.
515 D1 /5 SHR,r/m32 Unsigned divide r/m32 by 2, 1 time.
516 D3 /5 SHR,r/m32,CL Unsigned divide r/m32 by 2, CL times.
517 C1 /5 ib SHR,r/m32,imm8 Unsigned divide r/m32 by 2, imm8 times.
518 1C ib SBB,AL,imm8 Subtract with borrow imm8 from AL.
519 1D iw SBB,AX,imm16 Subtract with borrow imm16 from AX.
520 1D id SBB,EAX,imm32 Subtract with borrow imm32 from EAX.
521 80 /3 ib SBB,r/m8,imm8 Subtract with borrow imm8 from r/m8.
522 81 /3 iw SBB,r/m16,imm16 Subtract with borrow imm16 from r/m16.
523 81 /3 id SBB,r/m32,imm32 Subtract with borrow imm32 from r/m32.
524 83 /3 ib SBB,r/m16,imm8 Subtract with borrow sign-extended imm8 from r/m16.
525 83 /3 ib SBB,r/m32,imm8 Subtract with borrow sign-extended imm8 from r/m32.
526 18 /r SBB,r/m8,r8 Subtract with borrow r8 from r/m8.
527 19 /r SBB,r/m16,r16 Subtract with borrow r16 from r/m16.
528 19 /r SBB,r/m32,r32 Subtract with borrow r32 from r/m32.
529 1A /r SBB,r8,r/m8 Subtract with borrow r/m8 from r8.
530 1B /r SBB,r16,r/m16 Subtract with borrow r/m16 from r16.
531 1B /r SBB,r32,r/m32 Subtract with borrow r/m32 from r32.
532 AE SCAS,m8 Compare AL with byte at ES:(E)DI and set status flags.
533 AF SCAS,m16 Compare AX with word at ES:(E)DI and set status flags.
534 AF SCAS,m32 Compare EAX with doubleword at ES(E)DI and set status flags.
535 AE SCASB Compare AL with byte at ES:(E)DI and set status flags.
536 AF SCASW Compare AX with word at ES:(E)DI and set status flags.
537 AF SCASD Compare EAX with doubleword at ES:(E)DI and set status flags.
538 0F97 SETA,r/m8 Set byte if above (CF=0 and ZF=0).
539 0F93 SETAE,r/m8 Set byte if above or equal (CF=0).
540 0F92 SETB,r/m8 Set byte if below (CF=1).
541 0F96 SETBE,r/m8 Set byte if below or equal (CF=1 or ZF=1).
542 0F92 SETC,r/m8 Set if carry (CF=1).
543 0F94 SETE,r/m8 Set byte if equal (ZF=1).
544 0F9F SETG,r/m8 Set byte if greater (ZF=0 and SF=OF).
545 0F9D SETGE,r/m8 Set byte if greater or equal (SF=OF).
546 0F9C SETL,r/m8 Set byte if less (SF<>OF).
547 0F9E SETLE,r/m8 Set byte if less or equal (ZF=1 or SF<>OF).
548 0F96 SETNA,r/m8 Set byte if not above (CF=1 or ZF=1).
549 0F92 SETNAE,r/m8 Set byte if not above or equal (CF=1).
550 0F93 SETNB,r/m8 Set byte if not below (CF=0).
551 0F97 SETNBE,r/m8 Set byte if not below or equal (CF=0 and ZF=0).
552 0F93 SETNC,r/m8 Set byte if not carry (CF=0).
553 0F95 SETNE,r/m8 Set byte if not equal (ZF=0).
554 0F9E SETNG,r/m8 Set byte if not greater (ZF=1 or SF<>OF).
555 0F9C SETNGE,r/m8 Set if not greater or equal (SF<>OF).
556 0F9D SETNL,r/m8 Set byte if not less (SF=OF).
557 0F9F SETNLE,r/m8 Set byte if not less or equal (ZF=0 and SF=OF).
558 0F91 SETNO,r/m8 Set byte if not overflow (OF=0).
559 0F9B SETNP,r/m8 Set byte if not parity (PF=0).
560 0F99 SETNS,r/m8 Set byte if not sign (SF=0).
561 0F95 SETNZ,r/m8 Set byte if not zero (ZF=0).
562 0F90 SETO,r/m8 Set byte if overflow (OF=1).
563 0F9A SETP,r/m8 Set byte if parity (PF=1).
564 0F9A SETPE,r/m8 Set byte if parity even (PF=1).
565 0F9B SETPO,r/m8 Set byte if parity odd (PF=0).
566 0F98 SETS,r/m8 Set byte if sign (SF=1).
567 0F94 SETZ,r/m8 Set byte if zero (ZF=1).
568 F9 STC Set CF flag.
569 FD STD Set DF flag.
570 FB STI Set interrupt flag; external, maskable interrupts enabled at the end of the next instruction.
571 AA STOS,m8 Store AL at address ES:(E)DI.
572 AB STOS,m16 Store AX at address ES:(E)DI.
573 AB STOS,m32 Store EAX at address ES:(E)DI.
574 AA STOSB Store AL at address ES:(E)DI.
575 AB STOSW Store AX at address ES:(E)DI.
576 AB STOSD Store EAX at address ES:(E)DI.
577 2C ib SUB,AL,imm8 Subtract imm8 from AL.
578 2D iw SUB,AX,imm16 Subtract imm16 from AX.
579 2D id SUB,EAX,imm32 Subtract imm32 from EAX.
580 80 /5 ib SUB,r/m8,imm8 Subtract imm8 from r/m8.
581 81 /5 iw SUB,r/m16,imm16 Subtract imm16 from r/m16.
582 81 /5 id SUB,r/m32,imm32 Subtract imm32 from r/m32.
583 83 /5 ib SUB,r/m16,imm8 Subtract sign-extended imm8 from r/m16.
584 83 /5 ib SUB,r/m32,imm8 Subtract sign-extended imm8 from r/m32.
585 28 /r SUB,r/m8,r8 Subtract r8 from r/m8.
586 29 /r SUB,r/m16,r16 Subtract r16 from r/m16.
587 29 /r SUB,r/m32,r32 Subtract r32 from r/m32.
588 2A /r SUB,r8,r/m8 Subtract r/m8 from r8.
589 2B /r SUB,r16,r/m16 Subtract r/m16 from r16.
590 2B /r SUB,r32,r/m32 Subtract r/m32 from r32.
591 A8 ib TEST,AL,imm8 AND imm8 with AL; set SF, ZF, PF according to result.
592 A9 iw TEST,AX,imm16 AND imm16 with AX; set SF, ZF, PF according to result.
593 A9 id TEST,EAX,imm32 AND imm32 with EAX; set SF, ZF, PF according to result.
594 F6 /0 ib TEST,r/m8,imm8 AND imm8 with r/m8; set SF, ZF, PF according to result.
595 F7 /0 iw TEST,r/m16,imm16 AND imm16 with r/m16; set SF, ZF, PF according to result.
596 F7 /0 id TEST,r/m32,imm32 AND imm32 with r/m32; set SF, ZF, PF according to result.
597 84 /r TEST,r/m8,r8 AND r8 with r/m8; set SF, ZF, PF according to result.
598 85 /r TEST,r/m16,r16 AND r16 with r/m16; set SF, ZF, PF according to result.
599 85 /r TEST,r/m32,r32 AND r32 with r/m32; set SF, ZF, PF according to result.
600 90+rw XCHG,AX,16 Exchange r16 with AX.
601 90+rw XCHG,r16,AX Exchange AX with r16.
602 90+rd XCHG,EAX,r32 Exchange r32 with EAX.
603 90+rd XCHG,r32,EAX Exchange EAX with r32.
604 86 /r XCHG,r/m8,r8 Exchange r8 (byte register) with byte from r/m8.
605 86 /r XCHG,r8,r/m8 Exchange byte from r/m8 with r8 (byte register).
606 87 /r XCHG,r/m16,r16 Exchange r16 with word from r/m16.
607 87 /r XCHG,r16,r/m16 Exchange word from r/m16 with r16.
608 87 /r XCHG,r/m32,r32 Exchange r32 with doubleword from r/m32.
609 87 /r XCHG,r32,r/m32 Exchange doubleword from r/m32 with r32.
610 34 ib XOR,AL,imm8 AL XOR imm8.
611 35 iw XOR,AX,imm16 AX XOR imm16.
612 35 id XOR,EAX,imm32 EAX XOR imm32.
613 80 /6 ib XOR,r/m8,imm8 r/m8 XOR imm8.
614 81 /6 iw XOR,r/m16,imm16 r/m16 XOR imm16.
615 81 /6 id XOR,r/m32,imm32 r/m32 XOR imm32.
616 83 /6 ib XOR,r/m16,imm8 r/m16 XOR imm8 (sign-extended).
617 83 /6 ib XOR,r/m32,imm8 r/m32 XOR imm8 (sign-extended).
618 30 /r XOR,r/m8,r8 r/m8 XOR r8.
619 31 /r XOR,r/m16,r16 r/m16 XOR r16.
620 31 /r XOR,r/m32,r32 r/m32 XOR r32.
621 32 /r XOR,r8,r/m8 r8 XOR r/m8.
622 33 /r XOR,r16,r/m16 r16 XOR r/m16.
623 33 /r XOR,r32,r/m32 r32 XOR r/m32.
posted on 2009-02-14 20:21
陈梓瀚(vczh) 阅读(3114)
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