关于这个问题实在没有一个特别好的方法，基本方法还是来源于对intel手册的观察。因为指令表是从手册上面复制出来的，但是上面又没有标明66H前缀，怎么办呢？人肉找规律。这里贴出了区分的代码（进对于之前挑选出来的绝大多数x86与x87指令）以及生成后的一个很有规则的文件以供参考。
代码：
1 #include "..\..\..\..\VL++\Library\Platform\VL_Console.h"
2 #include "..\..\..\..\VL++\Library\Data\VL_System.h"
3 #include "..\..\..\..\VL++\Library\Data\VL_Stream.h"
4 #include "..\..\..\..\VL++\Library\Data\VL_DataAccess.h"
5 #include "..\..\..\..\VL++\Library\Data\Grammar2\VL_RegTools.h"
6 #include "..\..\..\..\VL++\Library\Data\Data\VL_Data_Map.h"
7
8 using namespace vl;
9 using namespace vl::platform;
10 using namespace vl::system;
11 using namespace vl::stream;
12 using namespace vl::grammar;
13
14 VUnicodeString FillStr(VUnicodeString String , VInt Length)
15 {
16 while(String.Length()<Length)
17 {
18 String+=L" ";
19 }
20 return String;
21 }
22
23 void GenerateProcessed(VUnicodeString In , VUnicodeString Out)
24 {
25 VL_FileStream FileIn(In,VL_FileStream::vomRead);
26 VL_FileStream FileOut(Out,VL_FileStream::vomWrite);
27 VL_StreamReader Reader(&FileIn,false);
28 VL_StreamWriter Writer(vceUtf16,true,&FileOut,false);
29
30 VUnicodeString BinCode=L"(?:<#BINCODE>[0-9A-F]{2})(\\s(?:<#BINCODE>[0-9A-F]{2}))*(\\+\\s*(?:<#BINCODE_PLUS>i|rb|rw|rd))?";
31 VUnicodeString BinExt=L"(\\s/(?:<#BINCODE_EXT>[0-7]|r))?(\\s(?:<#BINCODE_IMM>ib|iw|id|cb|cw|cd|cp))?";
32 VUnicodeString Name=L"\\s(?:<#NAME>[A-Z][A-Z0-9]*)";
33 VUnicodeString Param=L"(?:<#PARAM>AX|AL|EAX|CX|CL|ECX|CS|DS|ES|SS|FS|GS|[0-9]+|rel8|rel16|rel32|ptr16:16|ptr16:32|r8|r16|r32|imm8|imm16|imm32|r/m8|r/m16|r/m32|m2byte|m8|m16|m32|m64|m128|m16:16|m16:32|m16&32|m16&16|m32&32|moffs8|moffs16|moffs32|Sreg|m16int|m32int|m64int|m32fp|m64fp|m80fp|m|ST|ST\\(0\\)|ST\\(i\\))";
34 VUnicodeString Comment=L"\\s+(?:<#COMMENT>\\.*)";
35 VUnicodeString Expression=BinCode+BinExt+Name+L"(\\s"+Param+L"(,\\s*"+Param+L")*)?"+Comment;
36 VL_RegExp Regex(Expression,true);
37
38 VL_List<VL_RegExp::ResultPtr , false , VL_RegExp::Result*> ResultList;
39 VL_List<VL_RegExp::ResultPtr , false , VL_RegExp::Result*> Prefix16List;
40 VL_MultiMap<VUnicodeString , VL_RegExp::ResultPtr , false , VUnicodeString , VL_RegExp::Result*> ResultMap;
41
42 while(!Reader.IsEnd())
43 {
44 VUnicodeString Line=Reader.ReadLine();
45 if(Line!=L"")
46 {
47 VL_RegExp::ResultPtr MatchResult=Regex.MatchWhole(Line);
48 if(MatchResult->IsMatched())
49 {
50 VUnicodeString BinCode;
51 for(VInt i=0;i<MatchResult->GetStorageCount(L"BINCODE");i++)
52 {
53 BinCode+=MatchResult->GetStorage(L"BINCODE",i);
54 }
55 if(MatchResult->GetStorageCount(L"BINCODE_EXT")>0)
56 {
57 BinCode+=+L"/"+MatchResult->GetStorage(L"BINCODE_EXT",0);
58 }
59
60 ResultList.Add(MatchResult);
61 ResultMap.Add(BinCode,MatchResult);
62 }
63 else
64 {
65 GetConsole()->Write(L"[ERROR]"+Line+L"\r\n");
66 }
67 }
68 }
69
70 for(VInt i=0;i<ResultMap.KeyCount();i++)
71 {
72 VL_List<VL_RegExp::ResultPtr , false , VL_RegExp::Result*>& Values=ResultMap.ValueOfIndex(i);
73 if(Values.GetCount()>1)
74 {
75 VInt Count16=0;
76 VInt Count32=0;
77 VInt CountRemain=0;
78 VL_List<VL_RegExp::ResultPtr , false , VL_RegExp::Result*> Count16List;
79
80 for(VInt j=0;j<Values.GetCount();j++)
81 {
82 VInt Param16=0;
83 VInt Param32=0;
84 VInt ParamRemain=0;
85
86 VL_RegExp::ResultPtr Result=Values[j];
87 for(VInt k=0;k<Result->GetStorageCount(L"PARAM");k++)
88 {
89 VUnicodeString Param=Result->GetStorage(L"PARAM",k);
90 if(Param.SubString(Param.Length()-2,2)==L"16")
91 {
92 Param16++;
93 }
94 else if(Param.SubString(Param.Length()-2,2)==L"32")
95 {
96 Param32++;
97 }
98 else
99 {
100 ParamRemain++;
101 }
102 }
103 if(Param16)
104 {
105 if(Param32)
106 {
107 CountRemain++;
108 }
109 else
110 {
111 Count16++;
112 Count16List.Add(Result);
113 }
114 }
115 else if(Param32)
116 {
117 Count32++;
118 }
119 else
120 {
121 CountRemain++;
122 }
123 }
124 if(Count16==Count32 && CountRemain==0)
125 {
126 Prefix16List.Add(Count16List.Whole());
127 }
128 else
129 {
130 VUnicodeString Name=Values[0]->GetStorage(L"NAME",0);
131 if(Name.SubString(0,1)!=L"J" &&Name.SubString(0,3)!=L"SET" &&Name.SubString(0,4)!=L"LOOP" && Name!=L"XCHG" && Name!=L"SAL" && Name!=L"SHL")
132 {
133 if(Values.GetCount()==2)
134 {
135 Prefix16List.Add(Values[0]);
136 }
137 else
138 {
139 for(VInt j=0;j<Values.GetCount();j++)
140 {
141 GetConsole()->Write(L"[XXXX] "+Values[j]->GetText()+L"\r\n");
142 }
143 GetConsole()->Write(L"\r\n");
144 }
145 }
146 }
147 }
148 }
149
150 for(VInt i=0;i<ResultList.GetCount();i++)
151 {
152 VL_RegExp::ResultPtr MatchResult=ResultList[i];
153
154 VInt ParamOffset=0;
155 if(MatchResult->GetStorage(L"COMMENT",0)[0]==L'←')
156 {
157 ParamOffset=1;
158 }
159
160 VUnicodeString BinCode;
161 if(Prefix16List.Exists(MatchResult.Object()))
162 {
163 BinCode+=L"[66H]";
164 }
165 for(VInt i=0;i<MatchResult->GetStorageCount(L"BINCODE");i++)
166 {
167 BinCode+=MatchResult->GetStorage(L"BINCODE",i);
168 }
169 if(MatchResult->GetStorageCount(L"BINCODE_PLUS")>0)
170 {
171 BinCode+=L"+"+MatchResult->GetStorage(L"BINCODE_PLUS",0);
172 }
173 if(MatchResult->GetStorageCount(L"BINCODE_EXT")>0)
174 {
175 BinCode+=+L"/"+MatchResult->GetStorage(L"BINCODE_EXT",0);
176 }
177 if(MatchResult->GetStorageCount(L"BINCODE_IMM")>0)
178 {
179 BinCode+=+L"#"+MatchResult->GetStorage(L"BINCODE_IMM",0);
180 }
181
182 VUnicodeString Main;
183 Main+=MatchResult->GetStorage(L"NAME",0);
184 for(VInt i=0;i<MatchResult->GetStorageCount(L"PARAM")-ParamOffset;i++)
185 {
186 Main+=+L","+MatchResult->GetStorage(L"PARAM",i);
187 }
188
189 VUnicodeString Comment=MatchResult->GetStorage(L"COMMENT",0);
190 if(ParamOffset)
191 {
192 Comment=MatchResult->GetStorage(L"PARAM",MatchResult->GetStorageCount(L"PARAM")-1)+L" "+Comment;
193 }
194 Comment=L";"+Comment;
195
196 VUnicodeString NewLine=FillStr(BinCode,20)+FillStr(Main,30)+Comment;
197 Writer.WriteLine(NewLine);
198 }
199 }
200
201 void vlmain()
202 {
203 GetConsole()->SetTitle(L"Vczh Library++ 2.0 Assembler");
204 GetConsole()->SetTestMemoryLeaks(true);
205 GetConsole()->SetPauseOnExit(true);
206
207 VUnicodeString WorkData=VFileName(GetConsole()->GetAppPath()).MakeAbsolute(L"..\\..\\TestData\\").GetStrW();
208
209 VUnicodeString Original=WorkData+L"Ins_Original.txt";
210 VUnicodeString Processed=WorkData+L"Ins_Processed.txt";
211 GenerateProcessed(Original,Processed);
212 GetConsole()->Write(L"Stop generating\r\n");
213 }
结果：
1 14#ib ADC,AL,imm8 ;Add with carry imm8 to AL
2 [66H]15#iw ADC,AX,imm16 ;Add with carry imm16 to AX
3 15#id ADC,EAX,imm32 ;Add with carry imm32 to EAX
4 80/2#ib ADC,r/m8,imm8 ;Add with carry imm8 to r/m8
5 [66H]81/2#iw ADC,r/m16,imm16 ;Add with carry imm16 to r/m16
6 81/2#id ADC,r/m32,imm32 ;Add with CF imm32 to r/m32
7 [66H]83/2#ib ADC,r/m16,imm8 ;Add with CF sign-extended imm8 to r/m16
8 83/2#ib ADC,r/m32,imm8 ;Add with CF sign-extended imm8 into r/m32
9 10/r ADC,r/m8,r8 ;Add with carry byte register to r/m8
10 [66H]11/r ADC,r/m16,r16 ;Add with carry r16 to r/m16
11 11/r ADC,r/m32,r32 ;Add with CF r32 to r/m32
12 12/r ADC,r8,r/m8 ;Add with carry r/m8 to byte register
13 [66H]13/r ADC,r16,r/m16 ;Add with carry r/m16 to r16
14 13/r ADC,r32,r/m32 ;Add with CF r/m32 to r32
15 04#ib ADD,AL,imm8 ;Add imm8 to AL
16 [66H]05#iw ADD,AX,imm16 ;Add imm16 to AX
17 05#id ADD,EAX,imm32 ;Add imm32 to EAX
18 80/0#ib ADD,r/m8,imm8 ;Add imm8 to r/m8
19 [66H]81/0#iw ADD,r/m16,imm16 ;Add imm16 to r/m16
20 81/0#id ADD,r/m32,imm32 ;Add imm32 to r/m32
21 [66H]83/0#ib ADD,r/m16,imm8 ;Add sign-extended imm8 to r/m16
22 83/0#ib ADD,r/m32,imm8 ;Add sign-extended imm8 to r/m32
23 00/r ADD,r/m8,r8 ;Add r8 to r/m8
24 [66H]01/r ADD,r/m16,r16 ;Add r16 to r/m16
25 01/r ADD,r/m32,r32 ;Add r32 to r/m32
26 02/r ADD,r8,r/m8 ;Add r/m8 to r8
27 [66H]03/r ADD,r16,r/m16 ;Add r/m16 to r16
28 03/r ADD,r32,r/m32 ;Add r/m32 to r32
29 24#ib AND,AL,imm8 ;AL AND imm8
30 [66H]25#iw AND,AX,imm16 ;AX AND imm16
31 25#id AND,EAX,imm32 ;EAX AND imm32
32 80/4#ib AND,r/m8,imm8 ;r/m8 AND imm8
33 [66H]81/4#iw AND,r/m16,imm16 ;r/m16 AND imm16
34 81/4#id AND,r/m32,imm32 ;r/m32 AND imm32
35 [66H]83/4#ib AND,r/m16,imm8 ;r/m16 AND imm8 (sign-extended)
36 83/4#ib AND,r/m32,imm8 ;r/m32 AND imm8 (sign-extended)
37 20/r AND,r/m8,r8 ;r/m8 AND r8
38 [66H]21/r AND,r/m16,r16 ;r/m16 AND r16
39 21/r AND,r/m32,r32 ;r/m32 AND r32
40 22/r AND,r8,r/m8 ;r8 AND r/m8
41 [66H]23/r AND,r16,r/m16 ;r16 AND r/m16
42 23/r AND,r32,r/m32 ;r32 AND r/m32
43 [66H]62/r BOUND,r16,m16&16 ;Check if r16 (array index) is within bounds specified by m16&16
44 62/r BOUND,r32,m32&32 ;Check if r32 (array index) is within bounds specified by m32&32
45 [66H]0FBC BSF,r16,r/m16 ;Bit scan forward on r/m16
46 0FBC BSF,r32,r/m32 ;Bit scan forward on r/m32
47 [66H]0FBD BSR,r16,r/m16 ;Bit scan reverse on r/m16
48 0FBD BSR,r32,r/m32 ;Bit scan reverse on r/m32
49 0FC8+rd BSWAP,r32 ;Reverses the byte order of a 32-bit register.
50 [66H]0FA3 BT,r/m16,r16 ;Store selected bit in CF flag
51 0FA3 BT,r/m32,r32 ;Store selected bit in CF flag
52 [66H]0FBA/4#ib BT,r/m16,imm8 ;Store selected bit in CF flag
53 0FBA/4#ib BT,r/m32,imm8 ;Store selected bit in CF flag
54 [66H]0FBB BTC,r/m16,r16 ;Store selected bit in CF flag and complement
55 0FBB BTC,r/m32,r32 ;Store selected bit in CF flag and complement
56 [66H]0FBA/7#ib BTC,r/m16,imm8 ;Store selected bit in CF flag and complement
57 0FBA/7#ib BTC,r/m32,imm8 ;Store selected bit in CF flag and complement
58 [66H]0FB3 BTR,r/m16,r16 ;Store selected bit in CF flag and clear
59 0FB3 BTR,r/m32,r32 ;Store selected bit in CF flag and clear
60 [66H]0FBA/6#ib BTR,r/m16,imm8 ;Store selected bit in CF flag and clear
61 0FBA/6#ib BTR,r/m32,imm8 ;Store selected bit in CF flag and clear
62 [66H]0FAB BTS,r/m16,r16 ;Store selected bit in CF flag and set
63 0FAB BTS,r/m32,r32 ;Store selected bit in CF flag and set
64 [66H]0FBA/5#ib BTS,r/m16,imm8 ;Store selected bit in CF flag and set
65 0FBA/5#ib BTS,r/m32,imm8 ;Store selected bit in CF flag and set
66 [66H]E8#cw CALL,rel16 ;Call near, relative, displacement relative to next instruction
67 E8#cd CALL,rel32 ;Call near, relative, displacement relative to next instruction
68 [66H]FF/2 CALL,r/m16 ;Call near, absolute indirect, address given in r/m16
69 FF/2 CALL,r/m32 ;Call near, absolute indirect, address given in r/m32
70 [66H]9A#cd CALL,ptr16:16 ;Call far, absolute, address given in operand
71 9A#cp CALL,ptr16:32 ;Call far, absolute, address given in operand
72 [66H]FF/3 CALL,m16:16 ;Call far, absolute indirect, address given in m16:16
73 FF/3 CALL,m16:32 ;Call far, absolute indirect, address given in m16:32
74 [66H]98 CBW ;AX ← sign-extend of AL
75 98 CWDE ;EAX ← sign-extend of AX
76 F8 CLC ;Clear CF flag.
77 FC CLD ;Clear DF flag.
78 FA CLI ;Clear interrupt flag; interrupts disabled when interrupt flag cleared.
79 F5 CMC ;Complement CF flag.
80 [66H]0F47/r CMOVA,r16,r/m16 ;Move if above (CF=0 and ZF=0).
81 0F47/r CMOVA,r32,r/m32 ;Move if above (CF=0 and ZF=0).
82 [66H]0F43/r CMOVAE,r16,r/m16 ;Move if above or equal (CF=0).
83 0F43/r CMOVAE,r32,r/m32 ;Move if above or equal (CF=0).
84 [66H]0F42/r CMOVB,r16,r/m16 ;Move if below (CF=1).
85 0F42/r CMOVB,r32,r/m32 ;Move if below (CF=1).
86 [66H]0F46/r CMOVBE,r16,r/m16 ;Move if below or equal (CF=1 or ZF=1).
87 0F46/r CMOVBE,r32,r/m32 ;Move if below or equal (CF=1 or ZF=1).
88 [66H]0F42/r CMOVC,r16,r/m16 ;Move if carry (CF=1).
89 0F42/r CMOVC,r32,r/m32 ;Move if carry (CF=1).
90 [66H]0F44/r CMOVE,r16,r/m16 ;Move if equal (ZF=1).
91 0F44/r CMOVE,r32,r/m32 ;Move if equal (ZF=1).
92 [66H]0F4F/r CMOVG,r16,r/m16 ;Move if greater (ZF=0 and SF=OF).
93 0F4F/r CMOVG,r32,r/m32 ;Move if greater (ZF=0 and SF=OF).
94 [66H]0F4D/r CMOVGE,r16,r/m16 ;Move if greater or equal (SF=OF).
95 0F4D/r CMOVGE,r32,r/m32 ;Move if greater or equal (SF=OF).
96 [66H]0F4C/r CMOVL,r16,r/m16 ;Move if less (SF<>OF).
97 0F4C/r CMOVL,r32,r/m32 ;Move if less (SF<>OF).
98 [66H]0F4E/r CMOVLE,r16,r/m16 ;Move if less or equal (ZF=1 or SF<>OF).
99 0F4E/r CMOVLE,r32,r/m32 ;Move if less or equal (ZF=1 or SF<>OF).
100 [66H]0F46/r CMOVNA,r16,r/m16 ;Move if not above (CF=1 or ZF=1).
101 0F46/r CMOVNA,r32,r/m32 ;Move if not above (CF=1 or ZF=1).
102 [66H]0F42/r CMOVNAE,r16,r/m16 ;Move if not above or equal (CF=1).
103 0F42/r CMOVNAE,r32,r/m32 ;Move if not above or equal (CF=1).
104 [66H]0F43/r CMOVNB,r16,r/m16 ;Move if not below (CF=0).
105 0F43/r CMOVNB,r32,r/m32 ;Move if not below (CF=0).
106 [66H]0F47/r CMOVNBE,r16,r/m16 ;Move if not below or equal (CF=0 and ZF=0).
107 0F47/r CMOVNBE,r32,r/m32 ;Move if not below or equal (CF=0 and ZF=0).
108 [66H]0F43/r CMOVNC,r16,r/m16 ;Move if not carry (CF=0).
109 0F43/r CMOVNC,r32,r/m32 ;Move if not carry (CF=0).
110 [66H]0F45/r CMOVNE,r16,r/m16 ;Move if not equal (ZF=0).
111 0F45/r CMOVNE,r32,r/m32 ;Move if not equal (ZF=0).
112 [66H]0F4E/r CMOVNG,r16,r/m16 ;Move if not greater (ZF=1 or SF<>OF).
113 0F4E/r CMOVNG,r32,r/m32 ;Move if not greater (ZF=1 or SF<>OF).
114 [66H]0F4C/r CMOVNGE,r16,r/m16 ;Move if not greater or equal (SF<>OF.)
115 0F4C/r CMOVNGE,r32,r/m32 ;Move if not greater or equal (SF<>OF).
116 [66H]0F4D/r CMOVNL,r16,r/m16 ;Move if not less (SF=OF).
117 0F4D/r CMOVNL,r32,r/m32 ;Move if not less (SF=OF).
118 [66H]0F4F/r CMOVNLE,r16,r/m16 ;Move if not less or equal (ZF=0 and SF=OF).
119 0F4F/r CMOVNLE,r32,r/m32 ;Move if not less or equal (ZF=0 and SF=OF).
120 3C#ib CMP,AL,imm8 ;Compare imm8 with AL.
121 [66H]3D#iw CMP,AX,imm16 ;Compare imm16 with AX.
122 3D#id CMP,EAX,imm32 ;Compare imm32 with EAX.
123 80/7#ib CMP,r/m8,imm8 ;Compare imm8 with r/m8.
124 [66H]81/7#iw CMP,r/m16,imm16 ;Compare imm16 with r/m16.
125 81/7#id CMP,r/m32,imm32 ;Compare imm32 with r/m32.
126 [66H]83/7#ib CMP,r/m16,imm8 ;Compare imm8 with r/m16.
127 83/7#ib CMP,r/m32,imm8 ;Compare imm8 with r/m32.
128 38/r CMP,r/m8,r8 ;Compare r8 with r/m8.
129 [66H]39/r CMP,r/m16,r16 ;Compare r16 with r/m16.
130 39/r CMP,r/m32,r32 ;Compare r32 with r/m32.
131 3A/r CMP,r8,r/m8 ;Compare r/m8 with r8.
132 [66H]3B/r CMP,r16,r/m16 ;Compare r/m16 with r16.
133 3B/r CMP,r32,r/m32 ;Compare r/m32 with r32.
134 A6 CMPSB ;Compares byte at address DS:(E)SI with byte at address ES:(E)DI and sets the status flags accordingly.
135 [66H]A7 CMPSW ;Compares word at address DS:(E)SI with word at address ES:(E)DI and sets the status flags accordingly.
136 A7 CMPSD ;Compares doubleword at address DS:(E)SI with doubleword at address ES:(E)DI and sets the status flags accordingly.
137 [66H]99 CWD ;DX:AX ← sign-extend of AX
138 99 CDQ ;EDX:EAX ← sign-extend of EAX
139 FE/1 DEC,r/m8 ;Decrement r/m8 by 1.
140 [66H]FF/1 DEC,r/m16 ;Decrement r/m16 by 1.
141 FF/1 DEC,r/m32 ;Decrement r/m32 by 1.
142 [66H]48+rw DEC,r16 ;Decrement r16 by 1.
143 48+rd DEC,r32 ;Decrement r32 by 1.
144 F6/6 DIV,r/m8 ;Unsigned divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
145 [66H]F7/6 DIV,r/m16 ;Unsigned divide DX:AX by r/m16, with result stored in AX ← Quotient, DX ← Remainder.
146 F7/6 DIV,r/m32 ;Unsigned divide EDX:EAX by r/m32, with result stored in EAX ← Quotient, EDX ← Remainder.
147 D9E1 FABS ;Replace ST with its absolute value.
148 D8/0 FADD,m32fp ;Add m32fp to ST(0) and store result in ST(0).
149 DC/0 FADD,m64fp ;Add m64fp to ST(0) and store result in ST(0).
150 D8C0+i FADD,ST(0),ST(i) ;Add ST(0) to ST(i) and store result in ST(0).
151 DCC0+i FADD,ST(i),ST(0) ;Add ST(i) to ST(0) and store result in ST(i).
152 DEC0+i FADDP,ST(i),ST(0) ;Add ST(0) to ST(i), store result in ST(i), and pop the register stack.
153 DEC1 FADDP ;Add ST(0) to ST(1), store result in ST(1), and pop the register stack.
154 DA/0 FIADD,m32int ;Add m32int to ST(0) and store result in ST(0).
155 DE/0 FIADD,m16int ;Add m16int to ST(0) and store result in ST(0).
156 D9E0 FCHS ;Complements sign of ST(0)
157 DAC0+i FCMOVB,ST(0),ST(i) ;Move if below (CF=1).
158 DAC8+i FCMOVE,ST(0),ST(i) ;Move if equal (ZF=1).
159 DAD0+i FCMOVBE,ST(0),ST(i) ;Move if below or equal (CF=1 or ZF=1).
160 DAD8+i FCMOVU,ST(0),ST(i) ;Move if unordered (PF=1).
161 DBC0+i FCMOVNB,ST(0),ST(i) ;Move if not below (CF=0).
162 DBC8+i FCMOVNE,ST(0),ST(i) ;Move if not equal (ZF=0).
163 DBD0+i FCMOVNBE,ST(0),ST(i) ;Move if not below or equal (CF=0 and ZF=0).
164 DBD8+i FCMOVNU,ST(0),ST(i) ;Move if not unordered (PF=0).
165 D8/2 FCOM,m32fp ;Compare ST(0) with m32fp.
166 DC/2 FCOM,m64fp ;Compare ST(0) with m64fp.
167 D8D0+i FCOM,ST(i) ;Compare ST(0) with ST(i).
168 D8D1 FCOM ;Compare ST(0) with ST(1).
169 D8/3 FCOMP,m32fp ;Compare ST(0) with m32fp and pop register stack.
170 DC/3 FCOMP,m64fp ;Compare ST(0) with m64fp and pop register stack.
171 D8D8+i FCOMP,ST(i) ;Compare ST(0) with ST(i) and pop register stack.
172 D8D9 FCOMP ;Compare ST(0) with ST(1) and pop register stack.
173 DED9 FCOMPP ;Compare ST(0) with ST(1) and pop register stack twice.
174 DBF0+i FCOMI,ST,ST(i) ;Compare ST(0) with ST(i) and set status flags accordingly.
175 DFF0+i FCOMIP,ST,ST(i) ;Compare ST(0) with ST(i), set status flags accordingly, and pop register stack.
176 DBE8+i FUCOMI,ST,ST(i) ;Compare ST(0) with ST(i), check for ordered values, and set status flags accordingly.
177 DFE8+i FUCOMIP,ST,ST(i) ;Compare ST(0) with ST(i), check for ordered values, set status flags accordingly, and pop register stack.
178 D9FF FCOS ;Replace ST(0) with its cosine.
179 D9F6 FDECSTP ;Decrement TOP field in FPU status word.
180 D8/6 FDIV,m32fp ;Divide ST(0) by m32fp and store result in ST(0).
181 DC/6 FDIV,m64fp ;Divide ST(0) by m64fp and store result in ST(0).
182 D8F0+i FDIV,ST(0),ST(i) ;Divide ST(0) by ST(i) and store result in ST(0).
183 DCF8+i FDIV,ST(i),ST(0) ;Divide ST(i) by ST(0) and store result in ST(i).
184 DEF8+i FDIVP,ST(i),ST(0) ;Divide ST(i) by ST(0), store result in ST(i), and pop the register stack.
185 DEF9 FDIVP ;Divide ST(1) by ST(0), store result in ST(1), and pop the register stack.
186 DA/6 FIDIV,m32int ;Divide ST(0) by m32int and store result in ST(0).
187 DE/6 FIDIV,m16int ;Divide ST(0) by m64int and store result in ST(0).
188 D8/7 FDIVR,m32fp ;Divide m32fp by ST(0) and store result in ST(0)
189 DC/7 FDIVR,m64fp ;Divide m64fp by ST(0) and store result in ST(0)
190 D8F8+i FDIVR,ST(0),ST(i) ;Divide ST(i) by ST(0) and store result in ST(0)
191 DCF0+i FDIVR,ST(i),ST(0) ;Divide ST(0) by ST(i) and store result in ST(i)
192 DEF0+i FDIVRP,ST(i),ST(0) ;Divide ST(0) by ST(i), store result in ST(i), and pop the register stack
193 DEF1 FDIVRP ;Divide ST(0) by ST(1), store result in ST(1), and pop the register stack
194 DA/7 FIDIVR,m32int ;Divide m32int by ST(0) and store result in ST(0)
195 DE/7 FIDIVR,m16int ;Divide m16int by ST(0) and store result in ST(0)
196 DE/2 FICOM,m16int ;Compare ST(0) with m16int.
197 DA/2 FICOM,m32int ;Compare ST(0) with m32int.
198 DE/3 FICOMP,m16int ;Compare ST(0) with m16int and pop stack register.
199 DA/3 FICOMP,m32int ;Compare ST(0) with m32int and pop stack register.
200 DF/0 FILD,m16int ;Push m16int onto the FPU register stack.
201 DB/0 FILD,m32int ;Push m32int onto the FPU register stack.
202 DF/5 FILD,m64int ;Push m64int onto the FPU register stack.
203 D9F7 FINCSTP ;Increment the TOP field in the FPU status register.
204 DF/2 FIST,m16int ;Store ST(0) in m16int.
205 DB/2 FIST,m32int ;Store ST(0) in m32int.
206 DF/3 FISTP,m16int ;Store ST(0) in m16int and pop register stack.
207 DB/3 FISTP,m32int ;Store ST(0) in m32int and pop register stack.
208 DF/7 FISTP,m64int ;Store ST(0) in m64int and pop register stack.
209 DF/1 FISTTP,m16int ;Store ST as a signed integer (truncate) inm16int and pop ST.
210 DB/1 FISTTP,m32int ;Store ST as a signed integer (truncate) inm32int and pop ST.
211 DD/1 FISTTP,m64int ;Store ST as a signed integer(truncate) inm64int and pop ST.
212 D9/0 FLD,m32fp ;Push m32fp onto the FPU register stack.
213 DD/0 FLD,m64fp ;Push m64fp onto the FPU register stack.
214 DB/5 FLD,m80fp ;Push m80fp onto the FPU register stack.
215 D9C0+i FLD,ST(i) ;Push ST(i) onto the FPU register stack.
216 D9E8 FLD1 ;Push +1.0 onto the FPU register stack.
217 D9E9 FLDL2T ;Push log210 onto the FPU register stack.
218 D9EA FLDL2E ;Push log2e onto the FPU register stack.
219 D9EB FLDPI ;Push π onto the FPU register stack.
220 D9EC FLDLG2 ;Push log102 onto the FPU register stack.
221 D9ED FLDLN2 ;Push loge2 onto the FPU register stack.
222 D9EE FLDZ ;Push +0.0 onto the FPU register stack.
223 D8/1 FMUL,m32fp ;Multiply ST(0) by m32fp and store result in ST(0)
224 DC/1 FMUL,m64fp ;Multiply ST(0) by m64fp and store result in ST(0)
225 D8C8+i FMUL,ST(0),ST(i) ;Multiply ST(0) by ST(i) and store result in ST(0)
226 DCC8+i FMUL,ST(i),ST(0) ;Multiply ST(i) by ST(0) and store result in ST(i)
227 DEC8+i FMULP,ST(i),ST(0) ;Multiply ST(i) by ST(0), store result in ST(i), and pop the register stack
228 DEC9 FMULP ;Multiply ST(1) by ST(0), store result in ST(1), and pop the register stack
229 DA/1 FIMUL,m32int ;Multiply ST(0) by m32int and store result in ST(0)
230 DE/1 FIMUL,m16int ;Multiply ST(0) by m16int and store result in ST(0)
231 D9F3 FPATAN ;Replace ST(1) with arctan(ST(1)/ST(0)) and pop the register stack.
232 D9FC FRNDINT ;Round ST(0) to an integer.
233 D9FD FSCALE ;Scale ST(0) by ST(1).
234 D9FE FSIN ;Replace ST(0) with its sine.
235 D9FB FSINCOS ;Compute the sine and cosine of ST(0); replace ST(0) with the sine, and push the cosine onto the register stack.
236 D9FA FSQRT ;Computes square root of ST(0) and stores the result in ST(0).
237 D9/2 FST,m32fp ;Copy ST(0) to m32fp.
238 DD/2 FST,m64fp ;Copy ST(0) to m64fp.
239 DDD0+i FST,ST(i) ;Copy ST(0) to ST(i).
240 D9/3 FSTP,m32fp ;Copy ST(0) to m32fp and pop register stack.
241 DD/3 FSTP,m64fp ;Copy ST(0) to m64fp and pop register stack.
242 DB/7 FSTP,m80fp ;Copy ST(0) to m80fp and pop register stack.
243 DDD8+i FSTP,ST(i) ;Copy ST(0) to ST(i) and pop register stack.
244 9BDD/7 FSTSW,m2byte ;Store FPU status word at m2byte after checking forpending unmasked floating-point exceptions.
245 9BDFE0 FSTSW,AX ;Store FPU status word in AX register after checking forpending unmasked floating-point exceptions.
246 DD/7 FNSTSW,m2byte ;Store FPU status word at m2byte without checking forpending unmasked floating-point exceptions.
247 DFE0 FNSTSW,AX ;Store FPU status word in AX register without checking forpending unmasked floating-point exceptions.
248 D8/4 FSUB,m32fp ;Subtract m32fp from ST(0) and store result in ST(0).
249 DC/4 FSUB,m64fp ;Subtract m64fp from ST(0) and store result in ST(0).
250 D8E0+i FSUB,ST(0),ST(i) ;Subtract ST(i) from ST(0) and store result in ST(0).
251 DCE8+i FSUB,ST(i),ST(0) ;Subtract ST(0) from ST(i) and store result in ST(i).
252 DEE8+i FSUBP,ST(i),ST(0) ;Subtract ST(0) from ST(i), store result in ST(i), and pop register stack.
253 DEE9 FSUBP ;Subtract ST(0) from ST(1), store result in ST(1), and pop register stack.
254 DA/4 FISUB,m32int ;Subtract m32int from ST(0) and store result in ST(0).
255 DE/4 FISUB,m16int ;Subtract m16int from ST(0) and store result in ST(0).
256 D8/5 FSUBR,m32fp ;Subtract ST(0) from m32fp and store result in ST(0).
257 DC/5 FSUBR,m64fp ;Subtract ST(0) from m64fp and store result in ST(0).
258 D8E8+i FSUBR,ST(0),ST(i) ;Subtract ST(0) from ST(i) and store result in ST(0).
259 DCE0+i FSUBR,ST(i),ST(0) ;Subtract ST(i) from ST(0) and store result in ST(i).
260 DEE0+i FSUBRP,ST(i),ST(0) ;Subtract ST(i) from ST(0), store result in ST(i), and pop register stack.
261 DEE1 FSUBRP ;Subtract ST(1) from ST(0), store result in ST(1), and pop register stack.
262 DA/5 FISUBR,m32int ;Subtract ST(0) from m32int and store result in ST(0).
263 DE/5 FISUBR,m16int ;Subtract ST(0) from m16int and store result in ST(0).
264 D9E4 FTST ;Compare ST(0) with 0.0.
265 DDE0+i FUCOM,ST(i) ;Compare ST(0) with ST(i).
266 DDE1 FUCOM ;Compare ST(0) with ST(1).
267 DDE8+i FUCOMP,ST(i) ;Compare ST(0) with ST(i) and pop register stack.
268 DDE9 FUCOMP ;Compare ST(0) with ST(1) and pop register stack.
269 DAE9 FUCOMPP ;Compare ST(0) with ST(1) and pop register stack twice.
270 D9E5 FXAM ;Classify value or number in ST(0).
271 D9C8+i FXCH,ST(i) ;Exchange the contents of ST(0) and ST(i).
272 D9C9 FXCH ;Exchange the contents of ST(0) and ST(1).
273 D9F1 FYL2X ;Replace ST(1)with (ST(1) * log2ST(0)) and pop the register stack.
274 D9F9 FYL2XP1 ;Replace ST(1) with ST(1) * log2(ST(0) + 1.0) and pop the register stack.
275 F6/7 IDIV,r/m8 ;Signed divide AX by r/m8, with result stored in AL ← Quotient, AH ← Remainder.
276 [66H]F7/7 IDIV,r/m16 ;Signed divide DX:AX by r/m16, with result stored in AX ← Quotient, DX ← Remainder.
277 F7/7 IDIV,r/m32 ;Signed divide EDX:EAX by r/m32, with result stored in EAX ← Quotient, EDX ← Remainder.
278 F6/5 IMUL,r/m8 ;AX← AL * r/m byte.
279 [66H]F7/5 IMUL,r/m16 ;DX:AX ← AX * r/m word.
280 F7/5 IMUL,r/m32 ;EDX:EAX ← EAX * r/m doubleword.
281 [66H]0FAF/r IMUL,r16,r/m16 ;word register ← word register * r/m word.
282 0FAF/r IMUL,r32,r/m32 ;doubleword register ← doubleword register * r/m doubleword.
283 [66H]6B/r#ib IMUL,r16,r/m16,imm8 ;word register ← r/m16 * sign-extended immediate byte.
284 6B/r#ib IMUL,r32,r/m32,imm8 ;doubleword register ← r/m32 * sign-extended immediate byte.
285 [66H]69/r#iw IMUL,r16,r/m16,imm16 ;word register ← r/m16 * immediate word.
286 69/r#id IMUL,r32,r/m32,imm32 ;doubleword register ← r/m32 * immediate doubleword.
287 FE/0 INC,r/m8 ;Increment r/m byte by 1.
288 [66H]FF/0 INC,r/m16 ;Increment r/m word by 1.
289 FF/0 INC,r/m32 ;Increment r/m doubleword by 1.
290 [66H]40+rw INC,r16 ;Increment word register by 1.
291 40+rd INC,r32 ;Increment doubleword register by 1.
292 CC INT,3 ;Interrupt 3—trap to debugger.
293 CD#ib INT,imm8 ;Interrupt vector number specified by immediate byte.
294 CE INTO ;Interrupt 4—if overflow flag is 1.
295 77#cb JA,rel8 ;Jump short if above (CF=0 and ZF=0).
296 73#cb JAE,rel8 ;Jump short if above or equal (CF=0).
297 72#cb JB,rel8 ;Jump short if below (CF=1).
298 76#cb JBE,rel8 ;Jump short if below or equal (CF=1 or ZF=1).
299 72#cb JC,rel8 ;Jump short if carry (CF=1).
300 E3#cb JCXZ,rel8 ;Jump short if CX register is 0.
301 E3#cb JECXZ,rel8 ;Jump short if ECX register is 0.
302 74#cb JE,rel8 ;Jump short if equal (ZF=1).
303 7F#cb JG,rel8 ;Jump short if greater (ZF=0 and SF=OF).
304 7D#cb JGE,rel8 ;Jump short if greater or equal (SF=OF).
305 7C#cb JL,rel8 ;Jump short if less (SF<>OF).
306 7E#cb JLE,rel8 ;Jump short if less or equal (ZF=1 or SF<>OF).
307 76#cb JNA,rel8 ;Jump short if not above (CF=1 or ZF=1).
308 72#cb JNAE,rel8 ;Jump short if not above or equal (CF=1).
309 73#cb JNB,rel8 ;Jump short if not below (CF=0).
310 77#cb JNBE,rel8 ;Jump short if not below or equal (CF=0 and ZF=0).
311 73#cb JNC,rel8 ;Jump short if not carry (CF=0).
312 75#cb JNE,rel8 ;Jump short if not equal (ZF=0).
313 7E#cb JNG,rel8 ;Jump short if not greater (ZF=1 or SF<>OF).
314 7C#cb JNGE,rel8 ;Jump short if not greater or equal (SF<>OF).
315 7D#cb JNL,rel8 ;Jump short if not less (SF=OF).
316 7F#cb JNLE,rel8 ;Jump short if not less or equal (ZF=0 and SF=OF).
317 71#cb JNO,rel8 ;Jump short if not overflow (OF=0).
318 7B#cb JNP,rel8 ;Jump short if not parity (PF=0).
319 79#cb JNS,rel8 ;Jump short if not sign (SF=0).
320 75#cb JNZ,rel8 ;Jump short if not zero (ZF=0).
321 70#cb JO,rel8 ;Jump short if overflow (OF=1).
322 7A#cb JP,rel8 ;Jump short if parity (PF=1).
323 7A#cb JPE,rel8 ;Jump short if parity even (PF=1).
324 7B#cb JPO,rel8 ;Jump short if parity odd (PF=0).
325 78#cb JS,rel8 ;Jump short if sign (SF=1).
326 74#cb JZ,rel8 ;Jump short if zero (ZF = 1).
327 [66H]0F87#cw JA,rel16 ;Jump near if above (CF=0 and ZF=0).
328 [66H]0F83#cw JAE,rel16 ;Jump near if above or equal (CF=0).
329 [66H]0F82#cw JB,rel16 ;Jump near if below (CF=1).
330 [66H]0F86#cw JBE,rel16 ;Jump near if below or equal (CF=1 or ZF=1).
331 [66H]0F82#cw JC,rel16 ;Jump near if carry (CF=1).
332 [66H]0F84#cw JE,rel16 ;Jump near if equal (ZF=1).
333 [66H]0F84#cw JZ,rel16 ;Jump near if 0 (ZF=1).
334 [66H]0F8F#cw JG,rel16 ;Jump near if greater (ZF=0 and SF=OF).
335 0F87#cd JA,rel32 ;Jump near if above (CF=0 and ZF=0).
336 0F83#cd JAE,rel32 ;Jump near if above or equal (CF=0).
337 0F82#cd JB,rel32 ;Jump near if below (CF=1).
338 0F86#cd JBE,rel32 ;Jump near if below or equal (CF=1 or ZF=1).
339 0F82#cd JC,rel32 ;Jump near if carry (CF=1).
340 0F84#cd JE,rel32 ;Jump near if equal (ZF=1).
341 0F84#cd JZ,rel32 ;Jump near if 0 (ZF=1).
342 0F8F#cd JG,rel32 ;Jump near if greater (ZF=0 and SF=OF).
343 EB#cb JMP,rel8 ;Jump short, relative, displacement relative to next instruction.
344 [66H]E9#cw JMP,rel16 ;Jump near, relative, displacement relative to next instruction.
345 E9#cd JMP,rel32 ;Jump near, relative, displacement relative to next instruction.
346 [66H]FF/4 JMP,r/m16 ;Jump near, absolute indirect, address given in r/m16.
347 FF/4 JMP,r/m32 ;Jump near, absolute indirect, address given in r/m32.
348 [66H]EA#cd JMP,ptr16:16 ;Jump far, absolute, address given in operand.
349 EA#cp JMP,ptr16:32 ;Jump far, absolute, address given in operand.
350 [66H]FF/5 JMP,m16:16 ;Jump far, absolute indirect, address given in m16:16.
351 FF/5 JMP,m16:32 ;Jump far, absolute indirect, address given in m16:32.
352 [66H]8D/r LEA,r16,m ;Store effective address for m in register r16.
353 8D/r LEA,r32,m ;Store effective address for m in register r32.
354 AC LODSB ;Load byte at address DS:(E)SI into AL.
355 [66H]AD LODSW ;Load word at address DS:(E)SI into AX.
356 AD LODSD ;Load doubleword at address DS:(E)SI into EAX.
357 E2#cb LOOP,rel8 ;Decrement count; jump short if count ≠ 0.
358 E1#cb LOOPE,rel8 ;Decrement count; jump short if count ≠ 0 and ZF=1.
359 E1#cb LOOPZ,rel8 ;Decrement count; jump short if count ≠ 0 and ZF=1.
360 E0#cb LOOPNE,rel8 ;Decrement count; jump short if count ≠ 0 and ZF=0.
361 E0#cb LOOPNZ,rel8 ;Decrement count; jump short if count ≠ 0 and ZF=0.
362 88/r MOV,r/m8,r8 ;Move r8 to r/m8.
363 [66H]89/r MOV,r/m16,r16 ;Move r16 to r/m16.
364 89/r MOV,r/m32,r32 ;Move r32 to r/m32.
365 8A/r MOV,r8,r/m8 ;Move r/m8 to r8.
366 [66H]8B/r MOV,r16,r/m16 ;Move r/m16 to r16.
367 8B/r MOV,r32,r/m32 ;Move r/m32 to r32.
368 8C/r MOV,r/m16,Sreg ;Move segment register to r/m16.
369 8E/r MOV,Sreg,r/m16 ;Move r/m16 to segment register.
370 A0 MOV,AL,moffs8 ;Move byte at (seg:offset) to AL.
371 [66H]A1 MOV,AX,moffs16 ;Move word at (seg:offset) to AX.
372 A1 MOV,EAX,moffs32 ;Move doubleword at (seg:offset) to EAX.
373 A2 MOV,moffs8,AL ;Move AL to (seg:offset).
374 [66H]A3 MOV,moffs16,AX ;Move AX to (seg:offset).
375 A3 MOV,moffs32,EAX ;Move EAX to (seg:offset).
376 B0+rb MOV,r8,imm8 ;Move imm8 to r8.
377 [66H]B8+rw MOV,r16,imm16 ;Move imm16 to r16.
378 B8+rd MOV,r32,imm32 ;Move imm32 to r32.
379 C6/0 MOV,r/m8,imm8 ;Move imm8 to r/m8.
380 [66H]C7/0 MOV,r/m16,imm16 ;Move imm16 to r/m16.
381 C7/0 MOV,r/m32,imm32 ;Move imm32 to r/m32.
382 A4 MOVSB ;Move byte at address DS:(E)SI to address ES:(E)DI.
383 [66H]A5 MOVSW ;Move word at address DS:(E)SI to address ES:(E)DI.
384 A5 MOVSD ;Move doubleword at address DS:(E)SI to address ES:(E)DI.
385 [66H]0FB6/r MOVZX,r16,r/m8 ;Move byte to word with zero-extension.
386 0FB6/r MOVZX,r32,r/m8 ;Move byte to doubleword, zero-extension.
387 0FB7/r MOVZX,r32,r/m16 ;Move word to doubleword, zero-extension.
388 F6/4 MUL,r/m8 ;Unsigned multiply (AX ← AL * r/m8).
389 [66H]F7/4 MUL,r/m16 ;Unsigned multiply (DX:AX ← AX * r/m16).
390 F7/4 MUL,r/m32 ;Unsigned multiply (EDX:EAX ← EAX * r/m32).
391 F6/3 NEG,r/m8 ;Two's complement negate r/m8.
392 [66H]F7/3 NEG,r/m16 ;Two's complement negate r/m16.
393 F7/3 NEG,r/m32 ;Two's complement negate r/m32.
394 F6/2 NOT,r/m8 ;Reverse each bit of r/m8.
395 [66H]F7/2 NOT,r/m16 ;Reverse each bit of r/m16.
396 F7/2 NOT,r/m32 ;Reverse each bit of r/m32.
397 0C#ib OR,AL,imm8 ;AL OR imm8.
398 [66H]0D#iw OR,AX,imm16 ;AX OR imm16.
399 0D#id OR,EAX,imm32 ;EAX OR imm32.
400 80/1#ib OR,r/m8,imm8 ;r/m8 OR imm8.
401 [66H]81/1#iw OR,r/m16,imm16 ;r/m16 OR imm16.
402 81/1#id OR,r/m32,imm32 ;r/m32 OR imm32
403 [66H]83/1#ib OR,r/m16,imm8 ;r/m16 OR imm8 (sign-extended).
404 83/1#ib OR,r/m32,imm8 ;r/m32 OR imm8 (sign-extended).
405 08/r OR,r/m8,r8 ;r/m8 OR r8.
406 [66H]09/r OR,r/m16,r16 ;r/m16 OR r16.
407 09/r OR,r/m32,r32 ;r/m32 OR r32.
408 0A/r OR,r8,r/m8 ;r8 OR r/m8.
409 [66H]0B/r OR,r16,r/m16 ;r16 OR r/m16.
410 0B/r OR,r32,r/m32 ;r32 OR r/m32.
411 [66H]8F/0 POP,r/m16 ;Pop top of stack into m16; increment stack pointer.
412 8F/0 POP,r/m32 ;Pop top of stack into m32; increment stack pointer.
413 [66H]58+rw POP,r16 ;Pop top of stack into r16; increment stack pointer.
414 58+rd POP,r32 ;Pop top of stack into r32; increment stack pointer.
415 1F POP,DS ;Pop top of stack into DS; increment stack pointer.
416 07 POP,ES ;Pop top of stack into ES; increment stack pointer.
417 17 POP,SS ;Pop top of stack into SS; increment stack pointer.
418 0FA1 POP,FS ;Pop top of stack into FS; increment stack pointer.
419 0FA9 POP,GS ;Pop top of stack into GS; increment stack pointer.
420 [66H]61 POPA ;Pop DI, SI, BP, BX, DX, CX, and AX.
421 61 POPAD ;Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.
422 [66H]FF/6 PUSH,r/m16 ;Push r/m16.
423 FF/6 PUSH,r/m32 ;Push r/m32.
424 [66H]50+rw PUSH,r16 ;Push r16.
425 50+rd PUSH,r32 ;Push r32.
426 6A PUSH,imm8 ;Push imm8.
427 [66H]68 PUSH,imm16 ;Push imm16.
428 68 PUSH,imm32 ;Push imm32.
429 0E PUSH,CS ;Push CS.
430 16 PUSH,SS ;Push SS.
431 1E PUSH,DS ;Push DS.
432 06 PUSH,ES ;Push ES.
433 0FA0 PUSH,FS ;Push FS.
434 0FA8 PUSH,GS ;Push GS.
435 [66H]60 PUSHA ;Push AX, CX, DX, BX, original SP, BP, SI, and DI.
436 60 PUSHAD ;Push EAX, ECX, EDX, EBX, original ESP, EBP, ESI, and EDI.
437 D0/2 RCL,r/m8,1 ;Rotate 9 bits (CF, r/m8) left once.
438 D2/2 RCL,r/m8,CL ;Rotate 9 bits (CF, r/m8) left CL times.
439 C0/2#ib RCL,r/m8,imm8 ;Rotate 9 bits (CF, r/m8) left imm8 times.
440 [66H]D1/2 RCL,r/m16,1 ;Rotate 17 bits (CF, r/m16) left once.
441 [66H]D3/2 RCL,r/m16,CL ;Rotate 17 bits (CF, r/m16) left CL times.
442 [66H]C1/2#ib RCL,r/m16,imm8 ;Rotate 17 bits (CF, r/m16) left imm8 times.
443 D1/2 RCL,r/m32,1 ;Rotate 33 bits (CF, r/m32) left once.
444 D3/2 RCL,r/m32,CL ;Rotate 33 bits (CF, r/m32) left CL times.
445 C1/2#ib RCL,r/m32,imm8 ;Rotate 33 bits (CF, r/m32) left imm8 times.
446 D0/3 RCR,r/m8,1 ;Rotate 9 bits (CF, r/m8) right once.
447 D2/3 RCR,r/m8,CL ;Rotate 9 bits (CF, r/m8) right CL times.
448 C0/3#ib RCR,r/m8,imm8 ;Rotate 9 bits (CF, r/m8) right imm8 times.
449 [66H]D1/3 RCR,r/m16,1 ;Rotate 17 bits (CF, r/m16) right once.
450 [66H]D3/3 RCR,r/m16,CL ;Rotate 17 bits (CF, r/m16) right CL times.
451 [66H]C1/3#ib RCR,r/m16,imm8 ;Rotate 17 bits (CF, r/m16) right imm8 times.
452 D1/3 RCR,r/m32,1 ;Rotate 33 bits (CF, r/m32) right once.
453 D3/3 RCR,r/m32,CL ;Rotate 33 bits (CF, r/m32) right CL times.
454 C1/3#ib RCR,r/m32,imm8 ;Rotate 33 bits (CF, r/m32) right imm8 times.
455 D0/0 ROL,r/m8,1 ;Rotate 8 bits r/m8 left once.
456 D2/0 ROL,r/m8,CL ;Rotate 8 bits r/m8 left CL times.
457 C0/0#ib ROL,r/m8,imm8 ;Rotate 8 bits r/m8 left imm8 times.
458 [66H]D1/0 ROL,r/m16,1 ;Rotate 16 bits r/m16 left once.
459 [66H]D3/0 ROL,r/m16,CL ;Rotate 16 bits r/m16 left CL times.
460 [66H]C1/0#ib ROL,r/m16,imm8 ;Rotate 16 bits r/m16 left imm8 times.
461 D1/0 ROL,r/m32,1 ;Rotate 32 bits r/m32 left once.
462 D3/0 ROL,r/m32,CL ;Rotate 32 bits r/m32 left CL times.
463 C1/0#ib ROL,r/m32,imm8 ;Rotate 32 bits r/m32 left imm8 times.
464 D0/1 ROR,r/m8,1 ;Rotate 8 bits r/m8 right once.
465 D2/1 ROR,r/m8,CL ;Rotate 8 bits r/m8 right CL times.
466 C0/1#ib ROR,r/m8,imm8 ;Rotate 8 bits r/m16 right imm8 times.
467 [66H]D1/1 ROR,r/m16,1 ;Rotate 16 bits r/m16 right once.
468 [66H]D3/1 ROR,r/m16,CL ;Rotate 16 bits r/m16 right CL times.
469 [66H]C1/1#ib ROR,r/m16,imm8 ;Rotate 16 bits r/m16 right imm8 times.
470 D1/1 ROR,r/m32,1 ;Rotate 32 bits r/m32 right once.
471 D3/1 ROR,r/m32,CL ;Rotate 32 bits r/m32 right CL times.
472 C1/1#ib ROR,r/m32,imm8 ;Rotate 32 bits r/m32 right imm8 times.
473 C3 RET ;Near return to calling procedure.
474 CB RET ;Far return to calling procedure.
475 C2#iw RET,imm16 ;Near return to calling procedure and pop imm16 bytes from stack.
476 CA#iw RET,imm16 ;Far return to calling procedure and pop imm16 bytes from stack.
477 9E SAHF ;Load SF, ZF, AF, PF, and CF from AH into EFLAGS register.
478 D0/4 SAL,r/m8 ;Multiply r/m8 by 2, 1 time.
479 D2/4 SAL,r/m8,CL ;Multiply r/m8 by 2, CL times.
480 C0/4#ib SAL,r/m8,imm8 ;Multiply r/m8 by 2, imm8 times.
481 [66H]D1/4 SAL,r/m16 ;Multiply r/m16 by 2, 1 time.
482 [66H]D3/4 SAL,r/m16,CL ;Multiply r/m16 by 2, CL times.
483 [66H]C1/4#ib SAL,r/m16,imm8 ;Multiply r/m16 by 2, imm8 times.
484 D1/4 SAL,r/m32 ;Multiply r/m32 by 2, 1 time.
485 D3/4 SAL,r/m32,CL ;Multiply r/m32 by 2, CL times.
486 C1/4#ib SAL,r/m32,imm8 ;Multiply r/m32 by 2, imm8 times.
487 D0/7 SAR,r/m8 ;Signed divide* r/m8 by 2, 1 times.
488 D2/7 SAR,r/m8,CL ;Signed divide* r/m8 by 2, CL times.
489 C0/7#ib SAR,r/m8,imm8 ;Signed divide* r/m8 by 2, imm8 times.
490 [66H]D1/7 SAR,r/m16 ;Signed divide* r/m16 by 2, 1 time.
491 [66H]D3/7 SAR,r/m16,CL ;Signed divide* r/m16 by 2, CL times.
492 [66H]C1/7#ib SAR,r/m16,imm8 ;Signed divide* r/m16 by 2, imm8 times.
493 D1/7 SAR,r/m32 ;Signed divide* r/m32 by 2, 1 time.
494 D3/7 SAR,r/m32,CL ;Signed divide* r/m32 by 2, CL times.
495 C1/7#ib SAR,r/m32,imm8 ;Signed divide* r/m32 by 2, imm8 times.
496 D0/4 SHL,r/m8 ;Multiply r/m8 by 2, 1 time.
497 D2/4 SHL,r/m8,CL ;Multiply r/m8 by 2, CL times.
498 C0/4#ib SHL,r/m8,imm8 ;Multiply r/m8 by 2, imm8 times.
499 [66H]D1/4 SHL,r/m16 ;Multiply r/m16 by 2, 1 time.
500 [66H]D3/4 SHL,r/m16,CL ;Multiply r/m16 by 2, CL times.
501 [66H]C1/4#ib SHL,r/m16,imm8 ;Multiply r/m16 by 2, imm8 times.
502 D1/4 SHL,r/m32 ;Multiply r/m32 by 2, 1 time.
503 D3/4 SHL,r/m32,CL ;Multiply r/m32 by 2, CL times.
504 C1/4#ib SHL,r/m32,imm8 ;Multiply r/m32 by 2, imm8 times.
505 D0/5 SHR,r/m8 ;Unsigned divide r/m8 by 2, 1 time.
506 D2/5 SHR,r/m8,CL ;Unsigned divide r/m8 by 2, CL times.
507 C0/5#ib SHR,r/m8,imm8 ;Unsigned divide r/m8 by 2, imm8 times.
508 [66H]D1/5 SHR,r/m16 ;Unsigned divide r/m16 by 2, 1 time.
509 [66H]D3/5 SHR,r/m16,CL ;Unsigned divide r/m16 by 2, CL times.
510 [66H]C1/5#ib SHR,r/m16,imm8 ;Unsigned divide r/m16 by 2, imm8 times.
511 D1/5 SHR,r/m32 ;Unsigned divide r/m32 by 2, 1 time.
512 D3/5 SHR,r/m32,CL ;Unsigned divide r/m32 by 2, CL times.
513 C1/5#ib SHR,r/m32,imm8 ;Unsigned divide r/m32 by 2, imm8 times.
514 1C#ib SBB,AL,imm8 ;Subtract with borrow imm8 from AL.
515 [66H]1D#iw SBB,AX,imm16 ;Subtract with borrow imm16 from AX.
516 1D#id SBB,EAX,imm32 ;Subtract with borrow imm32 from EAX.
517 80/3#ib SBB,r/m8,imm8 ;Subtract with borrow imm8 from r/m8.
518 [66H]81/3#iw SBB,r/m16,imm16 ;Subtract with borrow imm16 from r/m16.
519 81/3#id SBB,r/m32,imm32 ;Subtract with borrow imm32 from r/m32.
520 [66H]83/3#ib SBB,r/m16,imm8 ;Subtract with borrow sign-extended imm8 from r/m16.
521 83/3#ib SBB,r/m32,imm8 ;Subtract with borrow sign-extended imm8 from r/m32.
522 18/r SBB,r/m8,r8 ;Subtract with borrow r8 from r/m8.
523 [66H]19/r SBB,r/m16,r16 ;Subtract with borrow r16 from r/m16.
524 19/r SBB,r/m32,r32 ;Subtract with borrow r32 from r/m32.
525 1A/r SBB,r8,r/m8 ;Subtract with borrow r/m8 from r8.
526 [66H]1B/r SBB,r16,r/m16 ;Subtract with borrow r/m16 from r16.
527 1B/r SBB,r32,r/m32 ;Subtract with borrow r/m32 from r32.
528 AE SCASB ;Compare AL with byte at ES:(E)DI and set status flags.
529 [66H]AF SCASW ;Compare AX with word at ES:(E)DI and set status flags.
530 AF SCASD ;Compare EAX with doubleword at ES:(E)DI and set status flags.
531 0F97 SETA,r/m8 ;Set byte if above (CF=0 and ZF=0).
532 0F93 SETAE,r/m8 ;Set byte if above or equal (CF=0).
533 0F92 SETB,r/m8 ;Set byte if below (CF=1).
534 0F96 SETBE,r/m8 ;Set byte if below or equal (CF=1 or ZF=1).
535 0F92 SETC,r/m8 ;Set if carry (CF=1).
536 0F94 SETE,r/m8 ;Set byte if equal (ZF=1).
537 0F9F SETG,r/m8 ;Set byte if greater (ZF=0 and SF=OF).
538 0F9D SETGE,r/m8 ;Set byte if greater or equal (SF=OF).
539 0F9C SETL,r/m8 ;Set byte if less (SF<>OF).
540 0F9E SETLE,r/m8 ;Set byte if less or equal (ZF=1 or SF<>OF).
541 0F96 SETNA,r/m8 ;Set byte if not above (CF=1 or ZF=1).
542 0F92 SETNAE,r/m8 ;Set byte if not above or equal (CF=1).
543 0F93 SETNB,r/m8 ;Set byte if not below (CF=0).
544 0F97 SETNBE,r/m8 ;Set byte if not below or equal (CF=0 and ZF=0).
545 0F93 SETNC,r/m8 ;Set byte if not carry (CF=0).
546 0F95 SETNE,r/m8 ;Set byte if not equal (ZF=0).
547 0F9E SETNG,r/m8 ;Set byte if not greater (ZF=1 or SF<>OF).
548 0F9C SETNGE,r/m8 ;Set if not greater or equal (SF<>OF).
549 0F9D SETNL,r/m8 ;Set byte if not less (SF=OF).
550 0F9F SETNLE,r/m8 ;Set byte if not less or equal (ZF=0 and SF=OF).
551 0F91 SETNO,r/m8 ;Set byte if not overflow (OF=0).
552 0F9B SETNP,r/m8 ;Set byte if not parity (PF=0).
553 0F99 SETNS,r/m8 ;Set byte if not sign (SF=0).
554 0F95 SETNZ,r/m8 ;Set byte if not zero (ZF=0).
555 0F90 SETO,r/m8 ;Set byte if overflow (OF=1).
556 0F9A SETP,r/m8 ;Set byte if parity (PF=1).
557 0F9A SETPE,r/m8 ;Set byte if parity even (PF=1).
558 0F9B SETPO,r/m8 ;Set byte if parity odd (PF=0).
559 0F98 SETS,r/m8 ;Set byte if sign (SF=1).
560 0F94 SETZ,r/m8 ;Set byte if zero (ZF=1).
561 F9 STC ;Set CF flag.
562 FD STD ;Set DF flag.
563 FB STI ;Set interrupt flag; external, maskable interrupts enabled at the end of the next instruction.
564 AA STOSB ;Store AL at address ES:(E)DI.
565 [66H]AB STOSW ;Store AX at address ES:(E)DI.
566 AB STOSD ;Store EAX at address ES:(E)DI.
567 2C#ib SUB,AL,imm8 ;Subtract imm8 from AL.
568 [66H]2D#iw SUB,AX,imm16 ;Subtract imm16 from AX.
569 2D#id SUB,EAX,imm32 ;Subtract imm32 from EAX.
570 80/5#ib SUB,r/m8,imm8 ;Subtract imm8 from r/m8.
571 [66H]81/5#iw SUB,r/m16,imm16 ;Subtract imm16 from r/m16.
572 81/5#id SUB,r/m32,imm32 ;Subtract imm32 from r/m32.
573 [66H]83/5#ib SUB,r/m16,imm8 ;Subtract sign-extended imm8 from r/m16.
574 83/5#ib SUB,r/m32,imm8 ;Subtract sign-extended imm8 from r/m32.
575 28/r SUB,r/m8,r8 ;Subtract r8 from r/m8.
576 [66H]29/r SUB,r/m16,r16 ;Subtract r16 from r/m16.
577 29/r SUB,r/m32,r32 ;Subtract r32 from r/m32.
578 2A/r SUB,r8,r/m8 ;Subtract r/m8 from r8.
579 [66H]2B/r SUB,r16,r/m16 ;Subtract r/m16 from r16.
580 2B/r SUB,r32,r/m32 ;Subtract r/m32 from r32.
581 A8#ib TEST,AL,imm8 ;AND imm8 with AL; set SF, ZF, PF according to result.
582 [66H]A9#iw TEST,AX,imm16 ;AND imm16 with AX; set SF, ZF, PF according to result.
583 A9#id TEST,EAX,imm32 ;AND imm32 with EAX; set SF, ZF, PF according to result.
584 F6/0#ib TEST,r/m8,imm8 ;AND imm8 with r/m8; set SF, ZF, PF according to result.
585 [66H]F7/0#iw TEST,r/m16,imm16 ;AND imm16 with r/m16; set SF, ZF, PF according to result.
586 F7/0#id TEST,r/m32,imm32 ;AND imm32 with r/m32; set SF, ZF, PF according to result.
587 84/r TEST,r/m8,r8 ;AND r8 with r/m8; set SF, ZF, PF according to result.
588 [66H]85/r TEST,r/m16,r16 ;AND r16 with r/m16; set SF, ZF, PF according to result.
589 85/r TEST,r/m32,r32 ;AND r32 with r/m32; set SF, ZF, PF according to result.
590 [66H]90+rw XCHG,AX,r16 ;Exchange r16 with AX.
591 [66H]90+rw XCHG,r16,AX ;Exchange AX with r16.
592 90+rd XCHG,EAX,r32 ;Exchange r32 with EAX.
593 90+rd XCHG,r32,EAX ;Exchange EAX with r32.
594 86/r XCHG,r/m8,r8 ;Exchange r8 (byte register) with byte from r/m8.
595 86/r XCHG,r8,r/m8 ;Exchange byte from r/m8 with r8 (byte register).
596 [66H]87/r XCHG,r/m16,r16 ;Exchange r16 with word from r/m16.
597 [66H]87/r XCHG,r16,r/m16 ;Exchange word from r/m16 with r16.
598 87/r XCHG,r/m32,r32 ;Exchange r32 with doubleword from r/m32.
599 87/r XCHG,r32,r/m32 ;Exchange doubleword from r/m32 with r32.
600 34#ib XOR,AL,imm8 ;AL XOR imm8.
601 [66H]35#iw XOR,AX,imm16 ;AX XOR imm16.
602 35#id XOR,EAX,imm32 ;EAX XOR imm32.
603 80/6#ib XOR,r/m8,imm8 ;r/m8 XOR imm8.
604 [66H]81/6#iw XOR,r/m16,imm16 ;r/m16 XOR imm16.
605 81/6#id XOR,r/m32,imm32 ;r/m32 XOR imm32.
606 [66H]83/6#ib XOR,r/m16,imm8 ;r/m16 XOR imm8 (sign-extended).
607 83/6#ib XOR,r/m32,imm8 ;r/m32 XOR imm8 (sign-extended).
608 30/r XOR,r/m8,r8 ;r/m8 XOR r8.
609 [66H]31/r XOR,r/m16,r16 ;r/m16 XOR r16.
610 31/r XOR,r/m32,r32 ;r/m32 XOR r32.
611 32/r XOR,r8,r/m8 ;r8 XOR r/m8.
612 [66H]33/r XOR,r16,r/m16 ;r16 XOR r/m16.
613 33/r XOR,r32,r/m32 ;r32 XOR r/m32.
614
posted on 2009-02-16 21:53
陈梓瀚(vczh) 阅读(2357)
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